CXL Refresh Controller Using Targeted Row Refresh Against Row Hammer
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Solution Overview
Problem
As computer devices decrease in size and increase in capacity, the row hammer phenomenon occurs, where the activation voltage of a certain row affects adjacent memory cells, compromising data integrity in memory devices lacking defense functions.
Innovation Solution
A CXL device with a refresh controller that sets a threshold value based on metadata to count command receptions, generating a targeted refresh signal when the count reaches the threshold, randomly selecting a row address for targeted refresh to mitigate row hammer effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density is increased to reduce device size, then device capacity increases, but row hammer vulnerability increases due to voltage distribution effects between adjacent rows
Solution Approach 1:
The refresh controller performs preliminary actions by counting commands before a row hammer attack can complete its damage. It monitors the number of commands targeting specific rows and proactively triggers a refresh operation on the target row before the voltage distribution effects can corrupt adjacent memory cells. This preliminary refresh action prevents the harmful effect from manifesting.
Solution Approach 2:
The system implements feedback by continuously monitoring command access patterns to memory rows. The refresh controller receives feedback about the number of commands targeting each row and uses this information to dynamically determine when to trigger targeted refresh operations. This feedback mechanism enables the system to respond to emerging row hammer threats in real-time.
2Reliability
If targeted refresh operations are implemented to defend against row hammer, then data integrity is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The refresh controller is designed with multi-functionality, serving both as a command counter and a refresh trigger generator. It universally handles multiple memory rows by maintaining counters for each row and can trigger refresh operations on any target row based on the counted commands. This universal design avoids the need for separate dedicated circuits for each row, reducing overall complexity.
Solution Approach 2:
The refresh controller performs self-service by autonomously monitoring command access patterns and automatically triggering refresh operations without external intervention. The system serves itself by using its own command counting capability to generate refresh signals, eliminating the need for additional external control logic or complex coordination circuits.
3Reliability
If all memory cells are refreshed at regular intervals to prevent row hammer, then security is improved, but productivity decreases due to increased refresh overhead
Solution Approach 1:
Instead of uniformly refreshing all memory rows, the system applies local quality by targeting only the specific row that has received a threshold number of commands. The refresh operation is localized to the vulnerable row identified by the counter, leaving other rows unaffected. This selective approach maintains security while minimizing the productivity impact of refresh operations.
Solution Approach 2:
The system performs partial action by refreshing only the necessary portion of memory (the targeted row) rather than performing a complete refresh of all memory cells. This partial refresh approach provides sufficient security against row hammer attacks on the vulnerable row while avoiding the excessive productivity loss that would result from refreshing the entire memory array.
Data Source
AI summary
A CXL device includes at least one memory; a CXL controller configured to receive a request to access the at least one memory via a CXL interface, and to output a memory identifier indicating a first memory of the at least one memory, a command and a row address of the first memory based on the request; and a refresh controller configured to store the row address as a target row address of the first memory and further configured to generate a targeted refresh signal based on a number of receptions of the command for refreshing the target row address in the first memory.