CXL Remote Memory Interface for Disaggregated Low-Latency Access
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Solution Overview
Problem
Existing computing systems face limitations in memory access due to cable length restrictions and high costs associated with equipping hosts with sufficient memory to handle varying demands, which can be costly and limit the available memory volume.
Innovation Solution
A system utilizing a cache coherent interface, such as Compute Express Link (CXL), coupled with a low latency remote direct memory access protocol (RDMA), allows hosts to dynamically access a memory pool outside the local rack, overcoming cable length limitations and enabling memory disaggregation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If cable length is increased to extend memory access distance, then memory volume and accessibility are improved, but signal integrity and connection reliability deteriorate
Solution Approach 1:
The patent introduces an interface circuit as an intermediary component between the processing circuit and memory. This interface circuit includes a first interface (CXL) connected to the processing circuit and a second interface (RDMA or Ethernet) connected to the memory, enabling extended memory access beyond direct cable length limitations while maintaining signal integrity through protocol conversion and intermediate processing.
2Quantity of substance
If host memory capacity is increased to handle varying demands, then memory availability is improved, but system cost increases
Solution Approach 1:
The patent implements a shared memory pool that can be dynamically accessed by multiple hosts through the interface circuit. Instead of each host requiring dedicated memory capacity, the system uses a universal memory resource that serves multiple purposes and multiple hosts, reducing total memory requirements and system cost while maintaining adequate memory availability for varying demands.
Solution Approach 2:
The system enables dynamic memory allocation where the interface circuit allows hosts to access memory resources on-demand rather than requiring static pre-allocation. This dynamic access pattern allows memory capacity to be shared and reallocated based on actual needs, reducing the total memory capacity required compared to static allocation schemes.
3Speed
If direct memory connection is used for low latency access, then access speed is improved, but cable length is limited
Solution Approach 1:
The patent segments the memory access path into multiple stages: the first interface (CXL) provides low-latency cache-coherent access for critical operations, while the second interface (RDMA/Ethernet) handles extended-distance memory access. This segmentation allows the system to maintain high-speed access for local operations while enabling longer cable lengths for remote memory resources.
Data Source
AI summary
A system with an interface for remote memory. In some embodiments, the system includes: an interface circuit having: a first interface, configured to be connected to a processing circuit; and a second interface, configured to be connected to memory, the first interface including a cache coherent interface, and the second interface being different from the first interface.