CXL Memory Controller ROM-Based ECC Predecoding for Fail Bit Maps

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing systems face challenges in efficiently managing and correcting errors in memory systems, particularly in shared memory environments where communication efficiency and access time are critical, due to the complexity of error bit mapping and correction.

Innovation Solution

A CXL memory controller equipped with a data conversion device that converts fail bit maps into error correction code (ECC) predecoded information, including address, error symbol position, and error type information, and an ECC engine for decoding, enhancing error correction performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional fail bit map processing is used in memory systems, then error detection capability is maintained, but error correction efficiency deteriorates due to complexity in mapping and correction operations

Engineering Contradiction:

Improveerror correction efficiencyVSAvoidcomplexity of error bit mapping and correction

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the error correction process by introducing a data conversion device that divides fail bit map processing into distinct stages: conversion to ECC predecoded information, storage in ROM, and final decoding by the ECC engine. This segmentation simplifies each component's function and improves overall error correction efficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The data conversion device acts as an intermediary between the fail bit map and the ECC engine. It converts the fail bit map into ECC predecoded information that includes address information, error symbol position information, and error type information, making the data suitable for efficient ECC processing without requiring complex mapping operations in the ECC engine itself.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If detailed error information is provided for precise error location, then decoding accuracy is improved, but data processing complexity increases

Engineering Contradiction:

Improveerror location precisionVSAvoiddata processing complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The data conversion device performs preliminary processing by converting the fail bit map into ECC predecoded information before it reaches the ECC engine. This preprocessed information includes pre-calculated address information, error symbol position information, and error type information, which reduces the processing burden on the ECC engine while maintaining high precision error location capability.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20260056834A1CXL memory controller, operating method therefor, and CXL memory device

Publication Date: 2026.02.26 SAMSUNG ELECTRONICS CO LTD

AI summary

A compute expression link (CXL) memory controller includes a data conversion device that receives a fail bit map and converts the fail bit map into error correction code (ECC) predecoded information in a symbol unit, a read only memory (ROM) that stores the ECC predecoded information, and an ECC engine that performs a decoding operation based on the ECC predecoded information. The ECC predecoded information includes address information indicating an address in which an error occurs, error symbol position information indicating one or more symbols in which the error occurs from among symbols corresponding to the address, and error type information indicating an error type of the one or more symbols.