CXL-Based Shared Memory Architecture for FPGA Accelerator Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Programmable logic devices, such as FPGAs, face challenges in reducing latency and improving throughput due to excessive data movement between host memory and accelerator memory during cryptographic and storage operations, leading to increased latency, memory bandwidth consumption, and power usage.
Innovation Solution
Implementing a Compute Express Link (CXL) protocol that allows the host and programmable device-based accelerators to directly access shared memory, reducing data movement by separating data and control planes and enabling efficient processing with hardware acceleration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is moved back and forth between host memory and accelerator memory for processing, then cryptographic and storage operations can be performed, but latency increases and throughput decreases
Solution Approach 1:
The patent merges the host memory and accelerator memory into a unified memory space, allowing the programmable logic device to access data without physical data movement between separate memory domains. This eliminates the back-and-forth data transfers that cause latency and reduce throughput.
Solution Approach 2:
The patent introduces a memory management unit or bridge that acts as an intermediary between the host and accelerator, enabling direct memory access and eliminating the need for repeated data movement between separate memory spaces.
2Productivity
If data is moved back and forth between host and accelerator, then operations can be offloaded, but memory bandwidth consumption increases
Solution Approach 1:
By combining host and accelerator memory into a single addressable space, the system eliminates redundant data transfers that consume memory bandwidth. The accelerator can process data in-place without requiring continuous data movement between separate memory domains.
3Productivity
If data is moved back and forth between host and accelerator, then operations can be performed, but power consumption increases
Solution Approach 1:
The unified memory architecture eliminates the energy-intensive data movement operations between separate host and accelerator memory spaces. The programmable logic device can access and process data directly in the shared memory space without triggering high-power DMA transfers.
4Adaptability or versatility
If multiple DMA channels are allocated for data movement, then more operations can be supported, but device complexity increases
Solution Approach 1:
The patent merges the memory spaces of host and accelerator, which fundamentally reduces the need for multiple DMA channels. With unified memory access, the system requires fewer DMA resources while supporting the same or greater number of concurrent operations.
Data Source
AI summary
Systems or methods of the present disclosure may provide receiving a request to perform an operation on data. A data payload of the data is then transmitted to a programmable logic device using a first transfer to enable offloading of at least a portion of the operation. Then, a descriptor corresponding to a storage location of the data payload in the programmable logic device is received. Using memory accesses one or more headers are added to the data payload in the storage location. Finally, the descriptor corresponding to the data payload is transmitted without the data payload to the programmable logic device to cause the programmable logic device to transmit packets comprising the data payload and the one or more headers over a network.