CXL Smart Storage Device Accelerator Bypass
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Solution Overview
Problem
Modern storage devices face challenges with low bandwidth and long delays in data transfer due to PCIe protocols, leading to issues with coherency and memory sharing when connected to host devices like CPUs and GPUs.
Innovation Solution
A smart storage device utilizing a CXL interface with sub-protocols like CXL.io, CXL.cache, and CXL.mem to connect an accelerator circuit and storage controller directly, enabling efficient data access and computation acceleration without host intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If PCIe protocol is used to connect host devices to semiconductor devices, then compatibility and ease of connection are improved, but bandwidth is limited and delays increase
Solution Approach 1:
The patent introduces CXL as an intermediary protocol layer between the host device and storage device. The CXL interface acts as a mediator that enables direct high-speed communication while maintaining compatibility with existing PCIe infrastructure, thus resolving the contradiction between ease of connection and bandwidth requirements
Solution Approach 2:
The patent changes the communication protocol parameter from traditional PCIe to CXL, which fundamentally alters the data transfer capabilities. This parameter change enables higher bandwidth and lower latency while maintaining the same physical connection interface, resolving the bandwidth limitation issue
2Reliability
If PCIe protocol is used for data transfer, then system compatibility is maintained, but data transfer delays increase
Solution Approach 1:
CXL serves as an intermediary that bridges the gap between compatibility requirements and performance demands. It maintains compatibility with existing host devices while introducing optimized data transfer mechanisms that reduce latency, thus resolving the contradiction between system compatibility and data transfer speed
Solution Approach 2:
The patent implements preliminary actions through features like persistent memory and direct access capabilities, where data is prepared and positioned in advance during system initialization and operation. This reduces the time required for subsequent data transfers and computations, addressing the delay issue while maintaining compatibility
3Device complexity
If traditional storage architecture is used, then implementation simplicity is maintained, but coherency and memory sharing problems occur
Solution Approach 1:
The patent makes the storage device universal by enabling it to perform multiple functions: traditional storage operations plus acceleration computation and direct memory access. The CXL interface provides multi-functional capabilities that include memory sharing and coherence management, allowing a single device to handle diverse workloads without increasing implementation complexity
Solution Approach 2:
The storage device is designed to be self-sufficient with its own processor and memory, enabling it to autonomously manage data coherence and memory sharing without constant host intervention. This self-service capability maintains data consistency while simplifying the overall system implementation by eliminating the need for complex host-side coordination
4Ease of operation
If host device directly controls storage access, then control simplicity is maintained, but computation acceleration capability is limited
Solution Approach 1:
The patent segments the storage system into independent functional units: a host device for high-level control, an accelerator processor for computation, and a storage device for data storage. Each component has dedicated control pathways, allowing the storage device to be directly controlled by the accelerator without requiring host intervention, thus achieving both control simplicity and computation acceleration
Solution Approach 2:
The CXL interface acts as an intermediary that enables direct control pathways between the accelerator and storage device, bypassing the host device for computation-related operations. This mediator maintains the simplicity of host control for management functions while enabling direct acceleration computation through the CXL protocol
Data Source
AI summary
A smart storage device is provided. The smart storage device includes a smart interface connected to a host device. An accelerator circuit is connected to the smart interface through a data bus conforming to a CXL.cache protocol and a CXL.mem protocol. The accelerator circuit is configured to perform acceleration computation in response to a computation command of the host device. A storage controller is connected to the smart interface through a data bus conforming to a CXL.io protocol. The storage controller is configured to control a data access operation for a storage device in response to a data access command of the host device. The accelerator circuit is directly accessible to the storage device through an internal bus connected directly to the storage controller.