CXL Memory Services for Reliable Storage Access Queues

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Solution Overview

Problem

Existing solid-state drives (SSDs) are limited in their ability to provide both memory and storage services due to the constraints imposed by backup power sources, which restrict the amount of volatile memory that can be used, leading to inefficiencies in data preservation during power failures.

Innovation Solution

SSDs are configured with a portion of fast volatile memory to provide cache-coherent memory services and storage access queues, allowing them to function as both memory and storage devices, with the option of using non-volatile memory or volatile memory backed by a backup power source to ensure data preservation during power disruptions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If backup power sources are used to preserve data during power failures, then data reliability is improved, but device complexity and cost increase

Engineering Contradiction:
Improvedata preservation during power failureVSAvoidbackup power source requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the backup power source from the system by using non-volatile memory to store data permanently without requiring external power for data preservation. This eliminates the capacitor or battery components while maintaining data reliability during power failures.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the memory type parameter from volatile to non-volatile, fundamentally altering the power dependency characteristic. Non-volatile memory inherently preserves data without power, eliminating the need for backup power sources while maintaining data integrity.

Inventive Principle:
Principle #35Parameter changes

2Speed

If volatile memory is used for storage access queues, then access speed is improved, but data preservation capability deteriorates

Engineering Contradiction:
Improvestorage access queue speedVSAvoiddata preservation during power failure
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent changes the memory parameter from volatile to non-volatile for the storage access queues. This allows the queues to maintain high access speeds while inherently preserving data during power failures, as non-volatile memory retains data without power.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If external backup power sources are required, then data integrity is improved, but ease of operation deteriorates

Engineering Contradiction:
Improvedata integrity during power failureVSAvoidexternal connection requirements
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent removes the external backup power source requirement by using non-volatile memory's inherent data preservation capability. The SSD operates independently without external power connections for data integrity, simplifying the system architecture and ease of operation.

Inventive Principle:
Principle #2Taking out (Extraction)

4Reliability

If non-volatile memory is used for storage access queues, then data preservation is improved, but access speed deteriorates

Engineering Contradiction:
Improvedata preservation during power failureVSAvoidstorage access queue access speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent segments the memory system into non-volatile memory for permanent storage and uses the non-volatile memory's addressable space to create storage access queues. This segmentation allows data to be preserved in non-volatile memory while enabling queue-based access patterns that maintain operational efficiency.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250258775A1Data Storage Device with Memory Services for Storage Access Queues
Publication Date: 2025.08.14 MICRON TECHNOLOGY INC
  • US20250258775A1 patent drawing
  • US20250258775A1 patent drawing
  • US20250258775A1 patent drawing

AI summary

A computing device having a compute express link (CXL) connection between a memory sub-system and a host system and having storage access queues configured at least in part in the memory sub-system. The memory sub-system can attach, as a memory device, a portion of its fast random access memory over the connection to the host system. One or more storage access queues can be configured in the memory device. The host system can use a cache-coherent memory access protocol to communicate storage access messages over the connection to the random access memory of the memory sub-system. Optionally, the host system can have a memory with second storage access queues usable to access the storage services of the memory sub-system over the connection using a storage access protocol.