CXL Expansion Storage for Low-Latency Sparse Data Access
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Solution Overview
Problem
High latency in data reading processes, particularly in scenarios requiring high-performance frequent table lookup, leads to degraded memory access time performance due to TLB cache misses and DDR access delays, especially in sparse memory access scenarios with high miss rates.
Innovation Solution
Implementing a data processing device with a processor connected to an expansion storage apparatus via a Compute Express Link (CXL) interface, utilizing low-latency storage such as SRAM or off-chip QDR series storage to store to-be-accessed data, and configuring a high priority for request messages to ensure low-latency data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is stored in external storage space (e.g., TLB) to meet latency requirements, then data reading latency is reduced, but storage capacity is limited
Solution Approach 1:
The storage system is segmented into two parts: a small high-speed storage space (first storage space) for frequently accessed data to reduce latency, and a large capacity storage space (second storage space) for general data storage. This segmentation allows the system to simultaneously achieve low latency for critical data while maintaining adequate overall storage capacity.
Solution Approach 2:
Different storage spaces are assigned different characteristics: the first storage space is optimized for speed (low latency) to handle frequently accessed data, while the second storage space is optimized for capacity. This local quality differentiation allows each storage region to serve its specific purpose effectively.
2Speed
If TLB cache is used to translate virtual addresses to physical addresses, then data reading speed is increased, but memory access time performance is degraded when TLB miss rate is high
Solution Approach 1:
The system pre-loads frequently accessed data into the first storage space before it is actually needed, based on access patterns and predictions. This preliminary action ensures that when data is requested, it is already available in the fast storage space, preventing TLB misses and reducing memory access time.
Solution Approach 2:
The first storage space acts as an intermediary between the TLB and the main memory storage space. It serves as a buffer that stores frequently accessed data, allowing the TLB to quickly translate addresses without having to access the main memory, thus reducing the impact of TLB misses on overall memory access time.
3Loss of time
If expansion storage apparatus is connected through CXL interface, then low-latency access is achieved, but interface complexity is increased
Solution Approach 1:
The CXL interface acts as an intermediary layer that provides a standardized, low-latency connection between the processor and the expansion storage apparatus. It simplifies the interface complexity by providing a unified protocol that handles both data transfer and address translation, making the system easier to implement while maintaining low latency performance.
Data Source
AI summary
This disclosure discloses a data processing device and method. Specific solutions are as follows: The data processing device includes a processor and an expansion storage apparatus. The expansion storage apparatus is connected to the processor through a CXL interface, and the expansion storage apparatus is configured to store to-be-accessed data of the processor; and a highest priority is configured for a request message for obtaining the to-be-accessed data stored in the expansion storage apparatus. When receiving a request message for processing first data, the processor obtains to-be-accessed data corresponding to the first data from the expansion storage apparatus, to process the first data.