CXL Switch Coherence Agent for Low-Latency Cache Sharing

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Solution Overview

Problem

Existing CXL switches experience increased latency in data read/write operations due to the need for multiple CXL links for cache coherence management, impacting performance in applications with significant data sharing between devices.

Innovation Solution

Implementing a switch coherence agent (SCOH) in the CXL switch to manage cache coherence, reducing the number of CXL links required for cache coherence management and optimizing data access latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cache coherence is managed through multiple CXL links (device-to-switch, switch-to-host, switch-to-device), then cache coherence can be maintained, but data access latency increases

Engineering Contradiction:

Improvecache coherenceVSAvoiddata access latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the cache coherence management function into the CXL switch itself by integrating a coherence engine directly in the switch. This consolidation eliminates the need for separate coherence management paths through multiple links, allowing the switch to handle coherence requests locally and reduce the number of hops required for data access operations.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The CXL switch acts as an intermediary with embedded coherence management capabilities. By placing the coherence engine in the switch, it mediates between the host and devices, handling coherence protocols locally rather than requiring all coherence operations to traverse the entire path through multiple CXL links, thus reducing latency.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If a CXL switch relay's messages through three CXL links for cache coherence, then cache coherence can be maintained, but the complexity of data transmission increases

Engineering Contradiction:

Improvecache coherenceVSAvoiddata transmission path

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple CXL link segments into a unified transmission path by integrating the coherence engine in the switch. This merging reduces the effective number of separate transmission paths from three links to a more streamlined route, simplifying the data transmission architecture while preserving coherence.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The CXL switch is designed with multi-functionality, serving both as a data relay and as a coherence management engine. This universal design allows the switch to handle both data transmission and coherence protocol operations within the same device, reducing the need for separate dedicated paths and simplifying the overall system architecture.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260010478A1CXL switch supporting low latency cache coherence, CXL computing system, and operating method thereof

Publication Date: 2026.01.08 KOREA ADVANCED INST OF SCI & TECH

AI summary

Disclosed is a CXL computing system including a compute express link (CXL)-enabled host CPU, CXL devices, and a CXL switch connecting the host CPU and the CXL devices. The CXL switch includes a switch coherence agent that manages cache coherence of the CXL devices connected to a lower layer.