CXL Switch Board for Dynamic Memory-Processor Allocation
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Solution Overview
Problem
Current server technologies face limitations in dynamically reallocating resources based on workload due to the tight coupling of memory and processor, leading to reduced memory bandwidth per core and inefficient memory utilization.
Innovation Solution
A board for CXL data transmission with a control chip supporting the CXL protocol, featuring uplink and downlink ports, allows flexible allocation of processors and memory modules by connecting hosts, processors, and memory modules through PCIe or CXL protocols, enabling dynamic resource reallocation based on workload.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory and processor are tightly coupled within a server node, then memory bandwidth per core is guaranteed, but resource reallocation based on workload cannot be achieved
Solution Approach 1:
The patent segments memory resources from processor resources by introducing a CXL switch board that physically separates memory modules from processor nodes. This allows memory to be independently allocated and reallocated to different processors based on workload requirements, resolving the contradiction between guaranteed bandwidth and flexible reallocation.
Solution Approach 2:
The CXL switch board acts as an intermediary between processors and memory modules, enabling dynamic resource allocation while maintaining performance guarantees. The switch board manages data transmission routes and memory allocation, allowing flexible resource distribution without direct tight coupling between processors and memory.
2Productivity
If memory is always deployed within a server node, then memory utilization efficiency can be optimized, but resource sharing across multiple devices is limited
Solution Approach 1:
The patent implements universal resource sharing by enabling memory modules to serve multiple processors through the CXL switch board. The same memory resources can be dynamically allocated to different processors based on workload demands, achieving both high utilization efficiency and broad resource sharing capability across the computing system.
3Productivity
If the number of memory channels is increased to match CPU core growth, then memory bandwidth per core is maintained, but device complexity and cost increase
Solution Approach 1:
The patent merges memory resources from multiple sources into a shared pool managed by the CXL switch board. Instead of increasing memory channels for each processor, the system consolidates memory resources that can be dynamically allocated to multiple processors, reducing overall device complexity while maintaining adequate bandwidth per core.
Data Source
AI summary
A board for CXL data transmission, a method for data transmission control and a device are provided. The board for CXL data transmission includes: a control chip, where the control chip is a chip that supports an open interconnection standard CXL protocol, and uplink ports and downlink ports are deployed on the control chip; the uplink ports, connected to a host, where the host is a device that supports a Peripheral Component Interconnect Express (PCIe) protocol or a device that supports the CXL protocol; and the downlink ports, connected to a processor at least one of and a memory module, where the downlink ports are correspondingly connected to the uplink ports, and the host is configured to transmit data to the corresponding downlink ports through the uplink ports, to transmit the data to the processor at least one of and the memory module through the downlink ports.