CXL Switch P2P Communication Protocol Segmentation
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Solution Overview
Problem
Current Compute Express Link (CXL) specifications limit the use of multiple CXL-based accelerators behind a CXL switch, preventing efficient peer-to-peer communication and memory access in multi-XPU systems, which is crucial for applications like AI training and high-performance computing.
Innovation Solution
Implementing a CXL switch that enables direct peer-to-peer communication by determining the cacheability of memory access requests and routing them either directly to peer devices or through the host, using a hybrid technique that combines CXL.cache and CXL.mem protocols to support both bulk and low-bandwidth accesses, thereby facilitating efficient data transfer without host intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single CXL accelerator is used under a CPU root port according to current CXL specification, then the system follows the standard protocol implementation, but multiple CXL-based accelerators cannot be supported behind a CXL switch
Solution Approach 1:
The patent segments the CXL protocol handling into two distinct paths: CXL.cache protocol for peer-to-peer communication between accelerators and CXL.mem protocol for memory access through the host. This segmentation allows the CXL switch to support multiple accelerator types and communication patterns simultaneously, resolving the limitation of single-accelerator configurations while maintaining protocol compliance.
Solution Approach 2:
The CXL switch acts as an intermediary device that mediates between multiple CXL accelerators and the host CPU. It intelligently routes traffic by determining whether requests should be handled directly between peers (via CXL.cache) or through the host (via CXL.mem), enabling multi-accelerator support without overwhelming the host with all communication traffic.
2Reliability
If all memory access requests are routed through the host, then protocol compliance is maintained, but latency increases and host processor load increases
Solution Approach 1:
The CXL switch performs preliminary action by pre-determining the cacheability of memory access requests and pre-establishing routing paths. When a request is identified as uncacheable, the switch immediately routes it through the CXL.cache protocol directly between peers without involving the host, thus maintaining protocol compliance for cacheable accesses while minimizing latency for uncacheable accesses.
Solution Approach 2:
The system dynamically selects between two protocol paths (CXL.cache and CXL.mem) based on the cacheability attribute of each memory access request. This dynamic routing adapts to the specific characteristics of each access, optimizing latency for uncacheable accesses while preserving the reliability and coherence guarantees of the CXL.mem protocol for cacheable accesses.
3Productivity
If direct peer-to-peer communication is enabled between accelerators, then latency is reduced and performance is enhanced, but the system requires complex protocol conversion and routing logic
Solution Approach 1:
The CXL switch implements local quality by applying different protocol handling rules to different types of memory access requests based on their cacheability attributes. Uncacheable requests receive direct peer-to-peer treatment via CXL.cache for optimal performance, while cacheable requests follow the standard CXL.mem path through the host, allowing the switch to optimize performance where possible without compromising system-wide coherence.
Data Source
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AI summary
In an embodiment, an apparatus includes: a first downstream port to couple to a first peer device; a second downstream port to couple to a second peer device; and a peer-to-peer (PTP) circuit to receive a memory access request from the first peer device, the memory access request having a target associated with the second peer device, where the PTP circuit is to convert the memory access request from a coherent protocol to a memory protocol and send the converted memory access request to the second peer device. Other embodiments are described and claimed.