Scalable Address Decoding for CXL Type-2 Devices
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Solution Overview
Problem
Current server CPUs face scalability issues with memory latency and reduced configuration flexibility due to the need for multiple System Address Decoder (SAD) rules in flat address decoding schemes for CXL Type-2 devices, which limits the number of devices that can be supported and increases latency.
Innovation Solution
A scalable address decoding scheme with programmable interleave granularity, using a single SAD rule to map multiple CXL Type-2 devices, dynamically determining interleave granularity based on device population, and interleaving devices using higher order physical address bits to reduce the number of SAD rule entries and improve flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a flat address decoding scheme with multiple SAD rules is used for CXL Type-2 devices, then each device can be mapped independently, but the number of SAD rules increases, leading to increased memory latency and reduced scalability
Solution Approach 1:
The patent combines multiple SAD rules into a single SAD rule by implementing an interleaved address decoding scheme. Instead of having separate SAD rules for each CXL Type-2 device, the system uses one SAD rule that interleaves addresses across multiple devices, thereby reducing the number of SAD rules from N (number of devices) to 1, which directly reduces memory latency while maintaining the ability to support multiple devices
Solution Approach 2:
The patent segments the address space into interleaved portions that can be dynamically assigned to different CXL Type-2 devices. By using higher order physical address bits for interleaving, the system divides the address space in a way that allows a single SAD rule to efficiently route requests to multiple devices, resolving the contradiction between supporting multiple devices and minimizing latency
2Adaptability or versatility
If multiple SAD rules are provisioned to support future CXL devices, then the system can accommodate more devices, but the SAD rule table size increases, consuming more silicon resources and increasing latency
Solution Approach 1:
The patent implements a dynamic address decoding scheme where a single SAD rule can be reconfigured to support different numbers and configurations of CXL Type-2 devices. The interleaving granularity and address mapping are dynamically adjustable, allowing the system to adapt to future device additions without provisioning for worst-case scenarios, thereby maintaining a compact SAD rule table while ensuring future scalability
Solution Approach 2:
The single SAD rule is designed to serve multiple CXL Type-2 devices simultaneously through interleaved addressing. This universal SAD rule can dynamically adapt to different device configurations and capacities, making it multi-functional. The system can support various numbers of devices with different memory capacities using the same SAD rule structure, eliminating the need to provision multiple specialized SAD rules
Data Source
AI summary
Methods and apparatus relating to a scalable address decoding scheme for Compute Express Link™ or CXL™ Type-2 devices with programmable interleave granularity are described. In an embodiment, configurator logic circuitry determines an interleave granularity and an address range size for a plurality of devices coupled to a socket of a processor. A single System Address Decoder (SAD) rule for two or more of the plurality of the devices coupled to the socket of the processor is stored in memory. A memory access transaction directed at a first device from the plurality of devices is routed to the first device in accordance with the SAD rule. Other embodiments are also disclosed and claimed.