Cycle-Based FPGA Reconfiguration for Dynamic Logic Mapping
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Solution Overview
Problem
Conventional FPGA reconfiguration methods require several tens of cycles, limiting dynamic reconfiguration to functional module levels and making them ineffective for applications needing more precise timing, such as cycle-based processing.
Innovation Solution
A data processing apparatus with a reconfigurable logic circuit that uses cycle-based mapping information to reconfigure the logic circuit in each cycle, allowing for dynamic reconfiguration at the behavior state level by selecting and merging appropriate mapping information based on execution states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional FPGA reconfiguration methods are used, then reconfiguration can be performed at functional module level, but reconfiguration time is several tens of cycles which is too slow for cycle-based processing
Solution Approach 1:
The patent segments the reconfiguration process into cycle-based units by dividing the logic circuit into multiple reconfigurable regions that can be independently configured. Each region has its own configuration data that can be loaded and applied in specific cycles, enabling fine-grained temporal control of reconfiguration at the cycle level rather than requiring tens of cycles for entire functional modules.
Solution Approach 2:
The patent introduces a new dimension of control by adding cycle-based timing control to the reconfiguration process. Instead of only controlling reconfiguration at the functional module level, the system now controls reconfiguration in the time dimension at cycle granularity, allowing different regions to be reconfigured at different cycles to achieve precise timing control.
2Adaptability or versatility
If reconfiguration is performed at functional module level with 500-1000 cycles per configuration, then stability is maintained, but processing flexibility for cycle-based applications is lost
Solution Approach 1:
The patent makes the reconfiguration system dynamic by enabling runtime reconfiguration at cycle level. The logic circuit can change its configuration dynamically during operation based on control signals, allowing the system to adapt to different processing requirements in different cycles rather than being static with fixed 500-1000 cycle configurations.
Solution Approach 2:
The patent introduces configuration control units and control signals as intermediaries between the configuration data and the logic circuit. These control units manage the complex reconfiguration process by selectively loading and applying configuration data to specific reconfigurable regions at designated cycles, simplifying the overall control mechanism while enabling fine-grained reconfiguration.
3Measurement precision
If multiple reconfigurable regions are used with cycle-based mapping, then reconfiguration precision is improved to cycle level, but control information complexity increases
Solution Approach 1:
The patent merges control functions by integrating configuration control units within the reconfigurable logic circuit itself. The control signals for multiple reconfigurable regions are coordinated through a unified control mechanism that manages configuration loading and application timing, reducing the overall control information required compared to independent control for each region.
Solution Approach 2:
The patent prepares configuration data in advance for multiple reconfigurable regions, organizing it into cycle-based mapping information before runtime. This preliminary organization of configuration data allows the system to efficiently load and apply configurations at the appropriate cycles without requiring complex real-time control decisions, reducing the control information burden during execution.
Data Source
AI summary
There is provided a data processing apparatus (1) including a logic circuit (10) that is reconfigurable in each cycle and a library (2) that stores hardware control information (20). The hardware control information (20) includes a plurality of pieces of cycle-based mapping information (21) for individually mapping a plurality of cycle-based circuits, which each realize a function in each cycle for executing an application, onto the logic circuit (10) and configuration selection information (22) for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. The data processing apparatus (1) includes a control unit (11) that reconfigures at least part of the logic region (10) using at least one of the plurality of pieces of cycle-based mapping information (21) according to a request in each cycle based on the configuration selection information (22).