Performance Monitor Cycle Counter Overflow Handling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high frequency of processor clock cycles often leads to overflow in dedicated counters within performance monitor units, causing inaccurate count results due to suspension of count operations until overflow adjustments and recordings are made.
Innovation Solution
The proposed counting circuit employs a cycle counter and event counters that reset and continue counting from zero when reaching maximum, allowing for accurate total cycle counting by utilizing trigger signals and multiplexers to manage overflow independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a dedicated counter is used to count clock cycles, then the counting function is simple and direct, but the counter easily reaches its count maximum at high clock frequencies and overflow occurs frequently
Solution Approach 1:
The patent divides the counting function into two independent parts: a cycle counter that counts clock cycles and an event counter that counts overflow events. This segmentation allows each counter to operate independently with appropriate count ranges, preventing the single counter from overflowing while maintaining accurate total cycle counting.
Solution Approach 2:
The patent introduces a trigger signal as an intermediary mechanism. When the cycle counter reaches its maximum, it generates a trigger signal that activates the event counter. This intermediary trigger signal mechanism allows the system to detect and record overflow events without suspending the counting operation, maintaining continuity and accuracy.
2Reliability
If the count of the dedicated counter is adjusted and overflow is recorded to cope with overflow, then overflow can be handled, but the dedicated counter is suspended during adjustment and recordation which affects count operation accuracy
Solution Approach 1:
The patent ensures continuous counting operation by having the cycle counter keep counting clock cycles while the event counter separately tracks overflow events. The trigger signal mechanism activates the event counter without interrupting the cycle counter, maintaining continuous and accurate counting throughout the enablement duration.
Solution Approach 2:
By segmenting the counting functionality into independent cycle counter and event counter, the system can handle overflow conditions without suspending the overall counting operation. Each counter operates independently, allowing overflow recording to occur without affecting the continuity of cycle counting.
3Reliability
If the dedicated counter is suspended for overflow adjustment and recordation, then overflow can be managed, but the count operation result becomes inaccurate during suspension
Solution Approach 1:
The patent maintains continuous counting operation through the independent operation of cycle counter and event counter. The cycle counter continuously counts clock cycles while the event counter continuously tracks overflow events, ensuring that the total cycle count remains accurate and complete throughout the entire enablement duration without any suspension.
Solution Approach 2:
The trigger signal acts as an intermediary that enables the event counter to record overflow events without interrupting the cycle counter's operation. This intermediary mechanism allows overflow management to occur in parallel with continuous counting, preventing any suspension and ensuring始终保持 accurate count results.
Data Source
AI summary
The present invention discloses a counting circuit of a performance monitor unit, capable of preventing a cycle counter from being suspended due to the occurrence of an overflow. An embodiment of the counting circuit includes a cycle counter and an event counter. The cycle counter starts counting from a beginning number according to a cycle of a clock signal during enablement duration, and when a count of the cycle counter reaches a count maximum of the cycle counter during the enablement duration, the cycle counter changes a level of a trigger signal and then counts from the beginning number again. The event counter counts according to change of the level of the trigger signal. Accordingly, the counting circuit is operable to obtain a total cycle number of the clock signal in the enablement duration according to the count of the cycle counter and a count of the event counter.