Cycle-Cycle Detector for Clock Signal Mismatch Reduction
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Solution Overview
Problem
Conventional methods for reducing mismatch in combined clock signals introduce additional mismatches, such as offset in comparators or resolution of analog-digital converters, which affect the accuracy of the synthesized clock signal.
Innovation Solution
A circuit comprising a cycle-cycle detector, a digital-time converter, a demultiplexer, and a state machine that generates a tuning signal to adjust the delay time of the synthesized clock signal, converting the cycle difference index signal into parallel data signals to minimize mismatches among phase-shifted signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a frequency divider and comparator are used to detect and adjust clock signal mismatch, then the mismatch of input phase signals can be adjusted, but additional mismatch is introduced due to comparator offset and ADC resolution limitations
Solution Approach 1:
The patent replaces the conventional mechanical/electrical comparison system (comparators and ADCs) with a digital logic-based cycle difference detection system. The cycle-cycle detector uses digital counters and logic circuits to directly measure cycle differences between clock signals, eliminating the need for analog comparators and ADCs, thereby avoiding their inherent offset and resolution limitations.
Solution Approach 2:
The patent introduces a cycle difference index signal as an intermediary representation of clock signal mismatch. Instead of directly comparing analog clock signals with all their imperfections, the system converts the mismatch information into a digital index signal that can be processed without introducing additional analog errors, serving as a clean mediator between the clock signals and the adjustment mechanism.
2Manufacturing precision
If conventional mismatch adjustment methods are applied, then phase signal alignment can be improved, but comparator offset and ADC resolution introduce additional errors
Solution Approach 1:
The patent substitutes the analog measurement chain (comparators and ADCs) with a purely digital measurement system. The cycle-cycle detector uses digital logic to count and compare clock cycles, providing high-precision phase alignment measurement without the offset and quantization errors inherent in analog systems.
Solution Approach 2:
The patent implements a feedback mechanism where the cycle difference index signal is continuously fed back to adjust the phase alignment of input signals. This closed-loop digital feedback system enables precise and stable phase alignment while avoiding the error accumulation problems of analog feedback systems.
Data Source
AI summary
A circuit comprises a cycle-cycle detector, configured to receive a synthesized clock signal, and detect a cycle difference index signal between any two neighboring cycles of the synthesized clock signal, wherein the synthesized clock signal is combined by a plurality of phase shifted signals; a demultiplexer connected to the cycle-cycle detector, configured to convert the cycle difference index signal into a plurality of parallel data signals; and a first state machine, connected to both the demultiplexer and the cycle-cycle detector, configured to generate a tuning signal based on the parallel data signals, and feed the tuning signal back to the cycle-cycle detector; wherein the cycle-cycle detector is further configured to adjust delay time of the synthesized clock signal according to the tuning signal.