Cycle Deterministic Testing Asynchronous Chip FIFO Buffer
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Solution Overview
Problem
The challenge in performing cycle deterministic functional testing of computing designs with asynchronous clock domains is that outputs from chips may arrive before or after the expected time, leading to inaccurate testing at low frequencies or inefficient synchronous mode designs that consume hardware area and power.
Innovation Solution
The method involves using an observe bus to funnel data from within the chip to output pins, storing it in FIFO data buffers, and providing the data at a frequency synchronized to the tester clock, ensuring cycle deterministic testing without requiring an alternative clock mode, thus avoiding hardware area and power consumption issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the tester conducts testing at low frequency to ensure cycle deterministic output arrival, then the output arrives at the expected time, but the testing is not at-speed and cannot accurately test the chip
Solution Approach 1:
The patent uses FIFO buffers to pre-store output data from asynchronous clock domains before the tester reads it. This preliminary buffering action decouples the asynchronous production of data from the synchronous reading by the tester, allowing the tester to operate at full speed while maintaining cycle deterministic output delivery.
Solution Approach 2:
The FIFO buffer acts as an intermediary between the asynchronous clock domain and the synchronous tester. It mediates the timing mismatch by accepting data at asynchronous rates and providing data at synchronous rates, enabling both accurate at-speed testing and cycle deterministic output delivery.
2Manufacturing precision
If the chip uses synchronous mode design to enable cycle deterministic testing, then cycle deterministic testing is achieved, but hardware area and power consumption increase
Solution Approach 1:
The patent extracts the timing synchronization function from the core chip logic and places it in the testing apparatus using FIFO buffers. This separates the asynchronous operation of the chip from the synchronous requirements of the tester, eliminating the need for synchronous mode design hardware in the chip while still achieving cycle deterministic testing.
Solution Approach 2:
The FIFO buffer in the testing apparatus serves as an intermediary that handles the timing conversion, allowing the chip to operate in its native asynchronous mode without requiring additional synchronous mode design hardware, thus reducing hardware area while maintaining testing cycle determinism.
3Manufacturing precision
If the chip uses synchronous mode design for cycle deterministic testing, then testing synchronism is achieved, but power consumption increases
Solution Approach 1:
The patent extracts the timing synchronization functionality from the chip and relocates it to the testing apparatus. This allows the chip to remain in its power-efficient asynchronous operating mode while the tester handles the synchronous timing requirements, reducing overall power consumption while maintaining testing synchronism.
Solution Approach 2:
The FIFO buffer acts as a power-efficient intermediary that enables synchronous testing without requiring the chip to operate in power-consuming synchronous mode. The buffer handles all timing conversion, allowing the chip to stay in low-power asynchronous operation while achieving testing synchronism.
Data Source
AI summary
Implementations of the present disclosure involve an apparatus and/or method for performing cycle deterministic functional testing of a microprocessor or other computing design with one or more asynchronous clock domains. In general, the method/apparatus involves utilizing an observe bus within the microprocessor design to funnel data from within the chip design to an output bus. In addition, to ensure that the output from the chip is synchronized to a tester clock, the observe bus may feed the information from the observe bus to one or more first-in first-out (FIFO) data buffers. During testing, the data stored in the data buffers may be provided to the output pins of the chip at a rate synchronized to the tester clock such that the output appears to the testing apparatus as being cycle deterministic. Further, one or more mechanisms may be employed within the observe bus or circuit design to control the rate of input of data into the data buffers.