Cycle Stealing for Integrated Circuit Timing Slack Optimization
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Solution Overview
Problem
Current electronic design automation (EDA) methods for integrated circuits face challenges in optimizing slack times in semiconductor chip designs, as traditional cycle stealing algorithms are limited by available slack measurements and struggle to balance input and output slacks effectively, leading to suboptimal design improvements.
Innovation Solution
The method involves calculating input and output timing slacks, selectively adding temporary pessimism to specific latches to encourage optimization, and using cycle stealing to modify clock launch and data line arrival times, thereby improving output timing slack and achieving a balanced slack goal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional cycle stealing algorithms are used to optimize slack times, then some timing improvement is achieved, but the ability to balance input and output slacks effectively is limited, leading to suboptimal design improvements
Solution Approach 1:
The patent applies preliminary action by temporarily adding pessimism to output slacks before the optimization process. This pre-modification creates a more favorable condition for cycle stealing algorithms to work, allowing them to achieve better balance between input and output slacks. By预先 modifying the output slack values to be more conservative, the algorithm has more room to operate and can achieve better overall timing balance without violating actual timing constraints.
2Loss of time
If cycle stealing modifies clock launch and data line arrival times to improve output timing slack, then output timing slack increases, but additional optimization rounds are needed to achieve balanced slack goals
Solution Approach 1:
The patent implements feedback by using the results from cycle stealing optimization to inform subsequent optimization rounds. After cycle stealing improves output timing slack, the algorithm recalculates slacks and uses this feedback to guide further optimization efforts. This feedback loop allows the system to progressively achieve balanced slack goals more efficiently by learning from each optimization iteration and adjusting strategies accordingly.
Data Source
AI summary
A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.