Cyclic A/D Converter Reducing Reference Voltages
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Solution Overview
Problem
Existing A/D converters require multiple capacitors for differential amplification, leading to increased circuit area and accuracy issues in generating reference voltages, which affects linearity and accuracy in A/D conversion.
Innovation Solution
A cyclic A/D converter design that uses a single-end type operational amplifier circuit with three capacitors and a switching circuit to generate operational values, reducing the number of reference voltages needed by switching between two voltage signals to simulate three voltage levels, thereby minimizing circuit area and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a differential amplification type gain stage is used, then measurement precision is improved, but device complexity increases due to requiring two times the number of capacitors
Solution Approach 1:
The patent employs asymmetric capacitor configuration where capacitor C1 has capacitance αC and capacitor C2 has capacitance (1-α)C, allowing the single-end gain stage to achieve differential-like precision through unequal capacitance values rather than requiring symmetric differential pairs
Solution Approach 2:
Instead of using a differential amplifier structure to achieve precision, the patent inverts the approach by using a single-end amplifier with carefully designed capacitive feedback network to achieve the same precision effect with reduced component count
2Ease of manufacture
If resistance voltage division is used to generate reference voltages, then manufacturing ease is improved, but measurement precision deteriorates due to low accuracy of resistance ratio
Solution Approach 1:
The patent replaces the mechanical/resistive voltage division method with an electronic switching method using capacitors C1 and C2 controlled by switches SW1-SW4, generating reference voltages through capacitive charge redistribution rather than resistive division
Solution Approach 2:
The patent changes the reference voltage generation mechanism from fixed resistive ratios to dynamically switchable capacitive ratios, allowing precise control of voltage levels through switch positioning rather than relying on resistor tolerance
3Adaptability or versatility
If three reference voltages (VRM, VRP, zero) are provided by DA converter circuit, then adaptability is improved for cyclic operation, but device complexity increases
Solution Approach 1:
The patent makes the capacitive reference voltage generation network serve multiple functions: generating VRM, VRP, and zero reference voltages, while also providing feedback signals for the gain stage and enabling cyclic operation, thereby reducing the need for separate dedicated circuits
Solution Approach 2:
The patent merges the reference voltage generation function with the feedback network function, using the same capacitors C1 and C2 and switches SW1-SW4 to simultaneously provide reference voltages and feedback signals, reducing overall circuit complexity
Data Source
AI summary
A cyclic A/D converter which can reduce the number of reference voltages for D/A conversion is provided. The cyclic A/D converter (11) comprises a gain stage (15), an A/D converter circuit (17), a logic circuit (19), and a D/A converter circuit (21). In an operational action of the gain stage (15), an operational value (VOP) is generated by the use of an operational amplifier circuit (23) and capacitors (25, 27, 29). The gain stage (15) operates as receiving three kinds of voltage signal from the D/A converter circuit (21) by the switching of two kinds of voltage signal (VDA1, VDA2) to be applied to the capacitors (25, 27) in a switching circuit (31). That is, the D/A converter circuit (21) provides a voltage signal (VRH) to the capacitors (25, 27), in response to a value (D=2) of a digital signal (B0, B1), provides voltage signals (VRH, VRL) to the capacitors (25, 27), respectively, in response to a value (D=1) of the signal (B0, B1), and provides the voltage signal (VRL) to the capacitors (25, 27), in response to a value (D=0) of the signal (B0, B1).