Continuous-Time Cyclic ADC With Loop Delay Compensation

Solution Overview

Problem

Existing analog-to-digital converters require significant power consumption due to the use of sample-and-hold circuits, which also occupy a large hardware area and introduce loop delays.

Innovation Solution

A cyclic analog-to-digital converter operates without a sample-and-hold circuit, utilizing an input network with resistors and RC integrators in continuous time, and employs two compensation circuits to compensate for loop delays, reducing power consumption and hardware area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a sample-and-hold circuit is used in the analog-to-digital converter, then the converter can operate in discrete time with stable signal holding, but the power consumption increases and the hardware area occupied increases

Engineering Contradiction:

Improvesignal stabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent removes the sample-and-hold circuit from the analog-to-digital converter architecture, extracting the problematic component that causes high power consumption and large hardware area occupation, while maintaining the converter's core functionality through a simplified continuous-time architecture

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the operating parameter from discrete-time sampling to continuous-time processing, fundamentally altering how the converter handles analog signals. This parameter change eliminates the need for sample-and-hold circuits and their associated power consumption and area requirements

Inventive Principle:

Principle #35Parameter changes

2Reliability

If a sample-and-hold circuit is used in the analog-to-digital converter, then the converter can operate in discrete time with stable signal holding, but the hardware area occupied increases

Engineering Contradiction:

Improvesignal stabilityVSAvoidhardware area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes the sample-and-hold circuit from the analog-to-digital converter architecture, extracting the problematic component that causes high power consumption and large hardware area occupation, while maintaining the converter's core functionality through a simplified continuous-time architecture

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the operating parameter from discrete-time sampling to continuous-time processing, fundamentally altering how the converter handles analog signals. This parameter change eliminates the need for sample-and-hold circuits and their associated power consumption and area requirements

Inventive Principle:

Principle #35Parameter changes

3Productivity

If a sample-and-hold circuit is used in the analog-to-digital converter, then the converter can operate in discrete time, but loop delays are introduced

Engineering Contradiction:

Improveconversion capabilityVSAvoidloop delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent changes the operating parameter from discrete-time sampling to continuous-time processing, fundamentally altering how the converter handles analog signals. This parameter change eliminates the need for sample-and-hold circuits and their associated power consumption and area requirements

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements continuous-time operation throughout the signal processing chain, maintaining continuous action from input to output. This continuity eliminates the discrete-time interruptions and loop delays that occur with sampling and holding operations

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20260074706A1Cyclic analog-to-digital converter and integrated circuit including the same

Publication Date: 2026.03.12 SAMSUNG ELECTRONICS CO LTD

AI summary

Acyclic analog-to-digital converter includes an input network configured to receive a first analog signal and a first compensation signal, and to output a second analog signal based on the first analog signal and the first compensation signal, the input network including at least one resistor in a path for transmitting the first analog signal, the first and second analog signals being continuous signals, a quantizer configured to output a digital signal based on the second analog signal and a second compensation signal, a first compensation circuit configured to output the first compensation signal based on the digital signal, and a second compensation circuit configured to output the second compensation signal based on the digital signal.