Cyclic ADC Difference-Signal Scaling for Capacitor Mismatch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cyclic analog-to-digital converters face challenges with capacitor mismatch, operational amplifier offset voltage, clock feed-through, channel charge injection, and leakage currents, with existing solutions failing to adequately address capacitor mismatch effects on digital output signals.
Innovation Solution
The method involves generating a difference signal by multiplying the analog signal and a reference signal by the ratio of sampler and integrator capacitances, doubling the difference signal, shifting it by a bit-dependent reference signal, and using the shifted signal for the next cycle, while allowing proportional corruption of signals between phase groups to minimize the impact of capacitance ratio differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cyclic AD conversion is implemented with sampler capacitor and integrator capacitor, then conversion speed and chip area are improved, but capacitor mismatch and parasitic capacitance effects cause errors in digital output signal
Solution Approach 1:
The patent uses feedback by comparing the digital output signal with the analog input signal and adjusting the conversion process accordingly. The error signal resulting from capacitor mismatch is fed back to correct the digital output, thereby compensating for the precision errors introduced by capacitor mismatch while maintaining high conversion speed.
Solution Approach 2:
The patent changes the parameters of the conversion process by dynamically adjusting the sampling and integration phases based on detected errors. By modifying the timing and amplitude parameters of the conversion cycles, the system compensates for capacitor mismatch effects and maintains high measurement precision during fast conversion.
2Measurement precision
If auto-zero techniques are used to cancel operational amplifier and comparator offset voltage, then offset voltage errors are reduced, but additional passive components and circuit complexity are required
Solution Approach 1:
The patent merges the offset cancellation function with the main conversion process by integrating auto-zero techniques into the existing sampler and integrator circuits. The offset compensation is performed using the same capacitors and operational amplifiers already present in the conversion path, eliminating the need for separate compensation circuits and reducing overall device complexity.
Solution Approach 2:
The patent makes the existing capacitors and operational amplifiers serve multiple functions: they perform both the primary conversion tasks (sampling and integration) and the offset cancellation function. This multi-functionality approach allows offset voltage compensation without adding dedicated passive components or increasing circuit complexity.
3Measurement precision
If fully differential structures are used to solve channel charge injection and leakage currents, then switch-related errors are reduced, but device complexity and area are increased
Solution Approach 1:
The patent applies the inversion principle by using the complementary nature of differential signals to cancel out charge injection and leakage effects. Instead of adding complex compensation circuits, the system inverts the problem by designing the conversion process to naturally reject these errors through differential signaling, where equal and opposite errors cancel each other out.
4Measurement precision
If clock pulses are tuned to cancel clock feed-through, then feed-through errors are reduced, but clock signal complexity and tuning requirements are increased
Solution Approach 1:
The patent uses periodic action by implementing periodic clock pulses with carefully controlled duty cycles and timing. The clock signal is designed to switch at specific intervals that allow the capacitor charges to settle properly, naturally canceling clock feed-through effects through the periodic nature of the switching without requiring complex tuning mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the dependency on capacitance ratios, improving bit generation accuracy by about 75% compared to prior art, and further reduces mismatch issues through iterative calibration and trimming processes, ensuring more precise capacitance matching.
Implementation Method 1
generating a difference signal multiplied by said ratio (C1/C2) from the analog signal and a reference signal
Implementation Method 2
a sampler capacitance (C1) and an integrator capacitance (C2)
Data Source
AI summary
Method and arrangement for cyclically AD converting an analog signal with a sampler capacitance and an integrator capacitance, comprising the steps of generating a difference signal multiplied by the ratio of said capacitances from the analog signal and a reference signal, deriving a digital bit from said difference signal, doubling the difference signal multiplied by said ratio, shifting said doubled signal by the reference signal multiplied by said ratio and using the shifted signal as difference signal multiplied by said ratio for the next cycle.