Two-Stage Cyclic A/D Converter for Lower-Accuracy Residue Bits
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Solution Overview
Problem
Existing A/D converters for image sensors face challenges in achieving high resolution with low noise and wide dynamic range, often requiring complex circuitry and high gain amplifiers, which complicates the circuit scale and accuracy requirements.
Innovation Solution
An A/D converter system that employs a first cyclic A/D converter circuit for generating upper N bits and a second A/D converter circuit for generating lower M bits, where the first stage performs cyclic conversion to reduce the accuracy requirements for the second stage, allowing for a simpler and more efficient circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single high-resolution A/D converter circuit is used to achieve high resolution with low noise and wide dynamic range, then the conversion accuracy is improved, but the circuit complexity and scale increase significantly
Solution Approach 1:
The patent divides the A/D conversion process into two separate stages: a first A/D converter circuit that converts the input signal to an intermediate digital value, and a second A/D converter circuit that converts the residue signal to the final digital value. This segmentation allows each converter to operate at lower resolution individually while achieving high overall resolution through combination, thereby reducing the circuit complexity and scale of each individual converter circuit.
2Reliability
If high gain amplifiers are used to reduce noise and improve dynamic range, then the signal quality is improved, but the circuit scale and accuracy requirements increase
Solution Approach 1:
The patent segments the conversion process into two stages where the first A/D converter handles the majority of the dynamic range conversion, and the second A/D converter processes the residue signal. This segmentation eliminates the need for high gain amplifiers to extend dynamic range, as each converter operates within a manageable range, thereby reducing circuit scale while maintaining signal quality.
Solution Approach 2:
The patent introduces a residue signal as an intermediary between the first and second A/D converter circuits. The residue signal represents the remaining analog portion after the first conversion stage, which is then fed to the second converter. This intermediary approach allows the system to achieve wide dynamic range without requiring excessively high gain amplifiers, thus reducing circuit scale while preserving signal fidelity.
3Measurement precision
If a complex circuit structure is used to achieve high resolution, then the conversion accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent divides the high-resolution conversion task into two separate lower-resolution conversion stages. Each A/D converter circuit operates at reduced resolution individually, which reduces the computational complexity and power consumption of each stage. The overall high resolution is achieved by combining the digital values from both stages, thereby reducing total power consumption while maintaining conversion resolution.
4Measurement precision
If high accuracy requirements are imposed on all converter stages, then the overall conversion accuracy is improved, but the circuit complexity and operation speed are affected
Solution Approach 1:
The patent segments the accuracy requirements across two conversion stages. The first A/D converter achieves partial accuracy for the most significant bits, while the second A/D converter achieves partial accuracy for the less significant bits using the residue signal. This segmentation allows each stage to operate with relaxed accuracy requirements compared to a single high-precision converter, thereby improving operation speed while maintaining overall conversion accuracy.
Data Source
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Figure 2(a)~2(b)
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AI summary
An object is to provide an A/D converter which uses a plurality of A/D converter circuits and can lower the A/D conversion accuracy in the A/D converter circuit for a lower digit by employing a cyclic A/D conversion scheme for an upper digit thereof. An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to 1/2L that in the A/D converter circuit 103.