Flexible Cyclic Addressing for AI Buffer Utilization
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Solution Overview
Problem
The limited capacity of buffers in AI processors restricts data access efficiency, as existing cyclic addressing schemes are inflexible and prone to data overwriting, especially when handling feature data of different sizes or growth rates.
Innovation Solution
Implementing a data processing method that sets flexible cyclic addressing ranges for input and output data buffers based on a pre-stored buffer allocation relationship, allowing different feature data to share buffers without overlapping addressing ranges, thereby improving buffer utilization and operation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a fixed cyclic addressing scheme is used for buffers, then the addressing mechanism is simple, but buffer utilization efficiency deteriorates when handling feature data of different sizes or growth rates
Solution Approach 1:
The patent implements dynamic cyclic addressing ranges for buffers, allowing the addressing range to be flexibly adjusted based on the actual size and growth rate of feature data. Instead of a fixed addressing scheme, the system dynamically determines the cyclic addressing range for each buffer, enabling efficient handling of feature data with varying sizes while maintaining buffer utilization efficiency.
2Productivity
If buffers are shared among different feature data, then buffer capacity utilization improves, but data overwriting risk increases with inflexible addressing schemes
Solution Approach 1:
The patent applies local quality by assigning different cyclic addressing ranges to different buffers sharing the same physical buffer space. Each buffer has its own locally optimized addressing range determined by the specific characteristics of its feature data, allowing multiple buffers to share physical space without data overwriting while maintaining high buffer capacity utilization.
3Productivity
If the buffer capacity is increased to accommodate all feature data, then data access efficiency improves, but the cost and complexity of the processor increases
Solution Approach 1:
The patent merges multiple logical buffers into a shared physical buffer space, using virtual buffer management with cyclic addressing ranges. This allows the system to accommodate all feature data efficiently by logically organizing data in the shared buffer, avoiding the need to increase physical buffer capacity while maintaining data access efficiency without increasing processor complexity.
Data Source
AI summary
This application discloses a data processing method and apparatus, an electronic device, and a storage medium. When execution is performed at an operation layer of a neural network model, based on a pre-stored buffer allocation relationship, a first address range for cyclic addressing is set for a first buffer corresponding to input data and a second address range for cyclic addressing is set for a second buffer corresponding to an output result. Subsequently, cyclic addressing can be performed in the first buffer based on the first address range for cyclic addressing, to read the input data for the operation layer; and cyclic addressing can be performed in the second buffer based on the second address range for cyclic addressing, to write the output result of the operation layer into the second buffer. In this way, efficiency of buffer utilization can be effectively improved, and further operation efficiency for the model is improved.