Cyclic Code Encoder Architecture for Multi-Throughput Parity Generation
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Solution Overview
Problem
Existing cyclic code encoding architectures are inflexible and require different design parameters for varying throughput capabilities, limiting their ability to support multiple throughput requirements efficiently.
Innovation Solution
A method and chip for cyclic code encoding that split payload symbols into multiple symbol sequences based on data rate thresholds, allowing a small bit width encoder to implement large bit width encoding, facilitating high-speed clock convergence and reducing implementation complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different design parameters are used for encoders with different throughput capabilities, then the implementation cost is minimized, but the encoding architecture becomes inflexible and cannot support multiple throughput requirements
Solution Approach 1:
The encoding architecture is segmented into a first encoding unit and a second encoding unit, where the first unit handles first payload data and the second unit handles second payload data. This segmentation allows the system to support multiple throughput capabilities (e.g., 200 Gbps and 400 Gbps) using a single unified architecture, resolving the contradiction between adaptability and complexity.
2Adaptability or versatility
If a single encoding architecture supports only one throughput capability, then the implementation cost is minimized, but the architecture lacks flexibility for varying data rates
Solution Approach 1:
The unified encoding architecture is designed to perform multiple functions by supporting different throughput capabilities through configurable parameters. The first and second encoding units can be configured to operate at different data rates (e.g., 200 Gbps or 400 Gbps), allowing a single architecture to serve multiple throughput requirements without requiring separate dedicated architectures for each rate, thus reducing implementation cost while maintaining versatility.
3Productivity
If payload symbols are split into multiple symbol sequences, then a small bit width encoder can implement large bit width encoding, but the encoding process becomes more complex
Solution Approach 1:
The payload symbols are segmented into multiple symbol sequences, where each sequence is processed by a corresponding encoding unit. This segmentation enables parallel processing of different data portions, increasing overall encoding speed and allowing small bit width encoders to effectively handle large bit width encoding tasks through coordinated operation of multiple units.
Solution Approach 2:
The first parity sequence and second parity sequence generated by the respective encoding units are merged to form the final parity symbols. This merging process combines the results from multiple parallel encoding operations, achieving high-speed encoding while managing complexity through systematic integration of the parallel processing results.
Data Source
AI summary
A method for cyclic code encoding includes: generating, based on a first symbol sequence related to a first part of symbols in the K payload symbols, a first parity sequence corresponding to the first symbol sequence; generating, based on a second symbol sequence related to a second part of symbols in the K payload symbols, a second parity sequence corresponding to the second symbol sequence, where the first part of symbols are different from the second part of symbols; and generating the (N−K) parity symbols based on the first parity sequence and the second parity sequence.