Successive Approximation ADC Using Cyclic DAC and Reversed Bit Memory
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Solution Overview
Problem
Successive approximation type A-to-D converters face challenges with high power consumption and large circuit size due to the need for a large number of capacitors in DACs, which reduces conversion speed and increases power consumption, especially in portable equipment where multiple radio systems with different specifications need to be integrated on a single chip.
Innovation Solution
The implementation of a successive approximation type A-to-D converter with a cyclic D-to-A converter, a comparator, and memory means that stores and reverses the output values, reducing circuit size and power consumption by using a smaller number of capacitors and flip-flops, and connecting multiple converters in parallel for high-speed conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of capacitors are used in the DAC to maintain conversion accuracy, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent divides the conversion process into multiple stages, using a first DAC with fewer capacitors for initial conversion and a second DAC for refining the result. This segmentation allows each DAC to use fewer capacitors while maintaining overall high conversion accuracy through the multi-stage process.
Solution Approach 2:
The patent introduces a time dimension by performing sequential conversions in multiple stages rather than attempting single-stage high-precision conversion. The first conversion result is processed further through a second DAC, effectively trading temporal complexity for reduced spatial complexity (fewer capacitors per DAC).
2Measurement precision
If a large number of capacitors are used in the DAC to maintain conversion accuracy, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The conversion task is segmented into multiple smaller conversion stages, each handled by a DAC with fewer capacitors. Since power consumption in DACs is proportional to the number of capacitors, this segmentation significantly reduces the power consumption of each individual DAC while achieving the same overall conversion accuracy through the multi-stage process.
Solution Approach 2:
Instead of performing a single exhaustive high-precision conversion that would require many capacitors and high power, the patent performs multiple partial conversions with fewer capacitors each. The cumulative effect of these partial conversions achieves the desired accuracy with much lower power consumption.
3Measurement precision
If more capacitors are used in the DAC, then measurement precision is improved, but operation speed decreases
Solution Approach 1:
The patent segments the conversion process into multiple faster, simpler conversion stages. Each stage uses fewer capacitors and thus operates faster, even though multiple stages are required. The overall conversion speed is improved because the parallel and sequential processing of multiple fast stages outweighs the latency of individual stages.
Solution Approach 2:
The first DAC performs a preliminary conversion that produces an intermediate result. This preliminary action reduces the burden on subsequent processing stages, allowing them to work with already-partially-converted data and achieve final high-precision conversion more quickly than a single-stage approach would allow.
Data Source
AI summary
A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.