Cyclic Memory Access Control via Modulo Timing
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Solution Overview
Problem
In multiprocessor systems, existing memory access control methods require expensive arbitration logic to prevent collisions, leading to increased footprint area and computing power usage, as well as halting of processors during simultaneous access attempts.
Innovation Solution
Implementing a cyclic allocation of memory access times for processors using modulo functions in their programs, allowing each processor to access a memory area at uniquely allocated times, eliminating the need for expensive hardware arbitration logic by ensuring only one processor can access at a time through carefully managed program addresses and jumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If arbitration logic is used to control memory access in multiprocessor systems, then memory access collisions are prevented, but hardware cost and footprint area increase
Solution Approach 1:
The patent replaces the mechanical hardware arbitration logic with a software-based solution using program instructions that execute modulo operations to determine memory access timing. Each processor executes instructions that calculate its access time based on a cyclic pattern, eliminating the need for complex hardware arbitration circuits while maintaining reliable collision-free memory access control.
2Reliability
If arbitration logic is used to control memory access, then collision prevention is achieved, but power consumption increases
Solution Approach 1:
The patent substitutes power-hungry hardware arbitration logic with energy-efficient software execution. The modulo-based timing calculation is performed using standard processor arithmetic units, which consume significantly less power than dedicated hardware arbitration circuits, thereby reducing overall system power consumption while maintaining reliable memory access control.
3Reliability
If traditional memory access control is used, then collision prevention is achieved, but processor halting occurs during simultaneous access attempts
Solution Approach 1:
The patent implements preliminary action by pre-calculating and embedding the cyclic access timing into the processor instructions before execution. Each processor knows in advance when it should access memory based on its assigned cyclic pattern, eliminating the need to halt during simultaneous access attempts. This allows processors to continue executing instructions without interruption while naturally avoiding memory conflicts through the predetermined timing scheme.
4Adaptability or versatility
If dual-port RAM with arbitration logic is used, then simultaneous access by two processors is enabled, but footprint area increases
Solution Approach 1:
The patent employs periodic action by implementing cyclic memory access patterns where processors take turns accessing shared memory at regular intervals determined by modulo operations. This time-division multiplexing approach allows multiple processors to effectively access the same memory resource without requiring simultaneous physical access ports, thereby enabling multi-processor adaptability while using standard single-port memory components with smaller footprint.
Data Source
AI summary
Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t≡[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.