Cyclic Pipeline ADC Without Sample-and-Hold Reset Overhead
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) face challenges in size, power consumption, and design complexity due to the inclusion of sample and hold units, which can limit their performance and efficiency in electronic devices.
Innovation Solution
The proposed ADC design eliminates the sample and hold unit, utilizing a converting module with a symmetrical capacitor network and selector circuit to generate intermediate codes and digital signals directly from analog inputs, reducing size and power consumption while improving accuracy through optimized capacitor arrangements and timing diagrams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a sample and hold unit is included in the ADC design, then the converter can maintain signal accuracy during conversion, but the device size and power consumption increase
Solution Approach 1:
The patent removes the sample and hold unit from the ADC architecture, extracting this component entirely from the system. The converting module directly processes analog input signals without requiring separate sampling and holding stages, thereby reducing device size while maintaining conversion accuracy through its direct conversion approach
Solution Approach 2:
The patent combines the functions of sampling, holding, and conversion into a single integrated converting module. The capacitor network and selector circuit perform multiple functions simultaneously, merging what were traditionally separate stages into one compact unit that reduces overall device area
2Measurement precision
If a sample and hold unit is included in the ADC design, then the converter can maintain signal accuracy during conversion, but power consumption increases
Solution Approach 1:
The patent extracts and removes the power-consuming sample and hold unit from the ADC design. By eliminating this separate functional block, the overall power consumption of the device is reduced while the converting module maintains signal accuracy through its direct conversion methodology
Solution Approach 2:
The patent merges sampling, holding, and conversion functions into a single power-efficient module. The integrated capacitor network and selector circuit perform all necessary operations in one unified structure, reducing the total power consumption compared to having separate dedicated circuits for each function
3Productivity
If conventional ADC design with sample and hold units is used, then the converter can handle signal conversion, but design complexity increases
Solution Approach 1:
The patent extracts and removes the complex sample and hold unit from the ADC design, simplifying the overall architecture. The converting module handles signal conversion directly without requiring the additional complexity of separate sampling and holding circuits, thereby reducing design complexity while maintaining conversion capability
Solution Approach 2:
The patent combines multiple conversion functions into a single integrated module with a capacitor network and selector circuit. This merging of functions into one unified structure reduces the number of separate components and interconnections, thereby simplifying the overall design while preserving full conversion capability
4Measurement precision
If frequent amplifier resets are performed in conventional ADCs, then the converter can maintain accuracy, but conversion speed decreases
Solution Approach 1:
The patent performs preliminary setup of the capacitor network and selector circuit to enable direct conversion without requiring intermediate amplifier resets. The converting module is pre-configured to handle the entire conversion process in one continuous operation, eliminating the need for frequent resets and thereby increasing conversion speed while maintaining accuracy
Solution Approach 2:
The patent enables continuous conversion operation by eliminating the interruptive amplifier reset cycles. The converting module maintains continuous operation with the capacitor network and selector circuit performing conversion duties without interruption, thereby improving conversion speed while preserving accuracy through the continuous conversion process
Data Source
AI summary
Some embodiments include apparatus and methods having a first module with a capacitor network configured to receive a sample of an analog input signal and an amplifier configured to couple to the capacitor network in a plurality of arrangements to successively generate a plurality of residue signals at an amplifier output node of the amplifier without resetting the amplifier between generation of least two of the plurality of residue signals, and a second module configured to generate a digital signal based on a plurality of intermediate codes generated from the sample signal and the plurality of residue signals, the digital signal including a digital value of the sample.