Cyclic RSD ADC Architecture With Variable Resolution Feedback
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Solution Overview
Problem
Conventional cyclic Redundant Signed Digit (RSD) A/D converters require multiple clock cycles and significant power and silicon area due to their architecture, which limits their efficiency in low power and small form factor applications.
Innovation Solution
A single-stage RSD A/D converter with a multi-bit/single-bit RSD stage that produces at least two digital bits during the first clock cycle and a single digital bit from the residual feedback signal during subsequent cycles, using a configuration with comparators and a logic circuit to generate digital output signals, achieving reduced capacitance, area, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional cyclic RSD A/D converter architecture is used, then the converter achieves high resolution, but it requires multiple clock cycles and significant power and silicon area
Solution Approach 1:
The converter architecture is segmented into a first RSD stage and a second RSD stage, where the first stage processes the analog input signal during the first clock cycle and the second stage processes the residual signal during the second clock cycle. This segmentation allows the system to achieve high resolution through multiple stages while reducing the complexity and area requirement of each individual stage compared to a single high-resolution stage.
Solution Approach 2:
The converter uses periodic clock cycles to perform conversion in discrete time intervals. The first RSD stage operates during the first clock cycle to produce initial digital bits, then the second RSD stage operates during the second clock cycle to produce additional digital bits from the residual signal. This periodic operation allows high resolution to be achieved through time-multiplexed processing rather than requiring all processing resources simultaneously, thereby reducing silicon area.
2Measurement precision
If a conventional cyclic RSD A/D converter architecture is used, then the converter achieves high resolution, but it consumes significant power
Solution Approach 1:
The power consumption is segmented across two clock cycles, with the first RSD stage consuming power during the first clock cycle and the second RSD stage consuming power during the second clock cycle. This temporal segmentation of power consumption allows the system to achieve high resolution while reducing peak power requirements and average power consumption compared to a single-stage architecture that would require all processing resources to operate simultaneously at full power.
3Use of energy by stationary object
If a single stage RSD A/D converter is used, then the converter reduces power and area, but it requires multiple clock cycles to complete conversion
Solution Approach 1:
The converter uses a periodic two-clock-cycle operation where the first clock cycle is dedicated to the first RSD stage producing initial digital bits and the second clock cycle is dedicated to the second RSD stage producing additional digital bits. This periodic structure efficiently utilizes time resources to achieve power and area reduction while completing the full conversion process in exactly two clock cycles, optimizing the trade-off between reduced resource consumption and conversion time.
4Area of stationary object
If a single stage RSD A/D converter is used, then the converter reduces silicon area, but it requires multiple clock cycles to complete conversion
Solution Approach 1:
The silicon area is segmented into two separate RSD stages that operate sequentially in time. The first RSD stage occupies the silicon area during the first clock cycle and the second RSD stage occupies the same or different silicon area during the second clock cycle. This temporal segmentation allows the system to achieve high resolution with reduced silicon area compared to a single large-stage architecture, as the full processing capability is not required simultaneously but is distributed across time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a 40% reduction in total capacitance and 25% reduction in area and power while maintaining the same sample rate and resolution as existing architectures, improving thermal noise performance.
Implementation Method 1
provide a residual feedback signal of the analog input signal at the analog input terminal
Implementation Method 2
each of the comparators operable to compare a selected one of the analog input signal and the residual voltage feedback signal to a predetermined voltage signal
Data Source
AI summary
A converter (200) adapted to convert an analog input signal into a digital output signal includes an analog input terminal (205) for receiving the analog input signal, a Redundant Signed Digit (RSD) stage (210) coupled to the analog input terminal, and a digital section (220). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.