Cyclic Write Cache Management for Non-Volatile Memory

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Solution Overview

Problem

Software-defined storage systems often have write cache management systems that are not compatible or optimized for the non-volatile memory technologies they use, leading to inefficiencies and compatibility issues.

Innovation Solution

Implementing a cyclic write cache structure with a set of pointers to manage write operations, allowing the system to be compatible with multiple types of non-volatile memory media hardware, such as SSD and PMEM, by consolidating small updates and minimizing metadata overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a software-defined storage system uses a write cache management system optimized for specific non-volatile memory hardware, then write performance and latency are improved, but compatibility with multiple types of non-volatile memory media hardware deteriorates

Engineering Contradiction:
Improvewrite performanceVSAvoidcompatibility with multiple non-volatile memory types
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The write cache management system is designed to be hardware-agnostic and compatible with multiple types of non-volatile memory media including SSDs and PMEM modules. The system uses a unified cyclic buffer structure with standardized pointer management that can operate across different memory technologies without requiring hardware-specific optimizations, thereby achieving multi-functionality and broad compatibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically adjusts write cache parameters such as buffer size, pointer update frequency, and metadata overhead based on the detected non-volatile memory type. By changing operational parameters rather than the fundamental management structure, the system maintains optimized write performance across different memory technologies while preserving compatibility.

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If metadata overhead is reduced to improve write operation speed, then write latency is decreased, but the ability to track and manage write cache data deteriorates

Engineering Contradiction:
Improvewrite latencyVSAvoidwrite cache tracking accuracy
Core Design Contradiction:
Loss of timeVSLoss of information

Solution Approach 1:

The write cache metadata is segmented into essential tracking fields only, separating critical information (head/tail pointers, cyclic buffer state) from optional detailed metadata. This segmentation allows the system to maintain accurate write cache tracking with minimal overhead by storing only the most critical tracking information in the metadata structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system extracts and stores only the essential tracking information needed for write cache management in the metadata, removing unnecessary metadata fields that would increase overhead. By taking out only the critical pointer information and cyclic buffer state, the system achieves low-latency writes while preserving sufficient tracking capability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If a cyclic buffer structure with multiple pointers is used to manage write cache, then write operation efficiency is improved, but the complexity of cache management increases

Engineering Contradiction:
Improvewrite operation efficiencyVSAvoidcache management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The cyclic buffer structure uses periodic wrapping of the write pointer to manage cache fullness automatically. When the write pointer reaches the end of the buffer, it wraps around to the beginning, creating a natural periodic cycle that simplifies overflow management. This periodic action eliminates the need for complex fullness checking logic while maintaining high write operation efficiency.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The multiple pointers in the cyclic buffer structure (read pointer, write pointer, wrap-around detection) enable the cache to self-manage its own fullness and emptiness states without external intervention. The pointers automatically track cache state and trigger appropriate actions (wrapping, flushing, etc.), reducing the complexity of external cache management logic.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11650920B1Write cache management
Publication Date: 2023.05.16 DELL PROD LP
  • US11650920B1 patent drawing
  • US11650920B1 patent drawing
  • US11650920B1 patent drawing

AI summary

A storage control system maintains a write cache in a non-volatile memory device of primary memory of a storage node. The write cache comprises a cyclic buffer and pointers to manage the write cache and track a tail location and head location of the write cache. The storage control system receives a write request from a host system, which comprises a data item to be written to primary storage. The received data item is written together with an associated metadata item at the head location of the write cache. The items in the write cache are arranged in a cyclic write order from the tail location to the head location. The storage control system sends an acknowledgment to the host system that the data item is successfully written to the primary storage, in response to the received data item and the associated metadata item being stored in the write cache.