Cyclical Cache Chains for Scan Test Bandwidth
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Solution Overview
Problem
Existing test architectures face challenges in reducing test application time while minimizing scan cell dependencies and pattern inflation, and ensuring compatibility with existing tester architectures.
Innovation Solution
The proposed test architecture incorporates a plurality of scan chains, cyclical cache chains, a decompressor, a compressor, and inverting logic, allowing for increased encoding bandwidth by mapping scan inputs to both scan chains and cyclical cache chains, with control logic to select between linear and cyclical modes, and using blocking and bypass circuitry to enhance bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the number of scan chains is increased to reduce test application time, then scan chain length is reduced and test application time decreases, but scan cell dependencies increase and pattern inflation occurs
Solution Approach 1:
The scan chains are divided into multiple segments with different shifting behaviors. Some segments shift every clock cycle while others shift periodically, allowing the system to maintain multiple scan chains without proportionally increasing dependencies across all chains. This segmentation reduces the overall scan cell dependencies while preserving the benefit of reduced scan chain lengths.
Solution Approach 2:
The patent implements periodic shifting where different scan chain segments shift at different rates. Some segments shift every clock cycle while others shift periodically (e.g., every other cycle). This periodic action allows the system to maintain high test data bandwidth through multiple scan chains while reducing the frequency with which dependencies propagate across all scan cells.
2Productivity
If the ratio of scan chains to scan inputs is increased to reduce test application time, then more scan chains are available for testing, but dependencies between values across scan cells increase
Solution Approach 1:
Scan chains are segmented into multiple groups that can be independently controlled. By dividing scan chains into segments with different shifting patterns, the system increases the effective ratio of scan chains to scan inputs while limiting the propagation of value dependencies within each segment, thereby maintaining test data bandwidth without proportionally increasing inter-scan-cell dependencies.
Solution Approach 2:
The patent introduces dynamic control over scan chain shifting behavior, where different segments can shift at different rates based on test requirements. This dynamic approach allows the system to adaptively manage the ratio of scan chains to scan inputs, increasing productivity when needed while controlling value dependencies through selective periodic shifting of specific segments.
3Loss of time
If scan chain length is reduced to decrease test application time, then test application time decreases, but the number of scan chains must increase which increases dependencies
Solution Approach 1:
By implementing periodic shifting where different scan chain segments shift at different rates, the patent allows the system to maintain a higher number of shorter scan chains without proportionally increasing the complexity of managing all scan chains. The periodic action reduces the effective dependency management overhead while preserving the benefit of reduced individual scan chain lengths.
Solution Approach 2:
The dynamic control mechanism allows the system to manage multiple short scan chains efficiently by enabling selective shifting of different segments. This dynamic approach reduces the operational complexity of managing numerous scan chains while maintaining the test application time benefits of shorter chain lengths.
Data Source
AI summary
A test architecture adds minimal area overhead and increases encoding bandwidth by using one or more cyclical cache chains for a set of the test patterns provided to the scan chains of the design. A multiplexer associated with a scan chain can be used to bypass a segment of the scan chain that includes unknown values. Blocking circuitry can be programmed to completely block one or more scan chains including unknown values. The test architecture can include control logic for selecting between a linear mode and a cyclical mode. In the linear mode, only top level scan inputs are mapped to the scan chains. In the cyclical mode, outputs of the plurality of cyclical cache chains and top level scan inputs are mapped to the scan chains.