Capacitorless DRAM Cylindrical Auxiliary Gate Leakage Reduction
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Solution Overview
Problem
Capacitorless dynamic random access memory (DRAM) faces challenges in maintaining sufficient retention time due to charge leakage from the channel body, which affects data storage efficiency.
Innovation Solution
The implementation of a capacitorless DRAM structure with cylindrical auxiliary gates and a bulk substrate, where the channel body is formed between source and drain regions, and a main gate is disposed over the channel body, with the cylindrical auxiliary gates being either electrically connected or insulated, and a method of fabricating this structure involving trench formation, ion implantation, and conductive layer patterning to enhance charge storage and retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitorless DRAM stores charges in a channel body of a substrate, then the device complexity is reduced by eliminating the capacitor, but the retention time becomes insufficient due to charge leakage
Solution Approach 1:
The channel body is segmented into different depth regions: a deeper central portion for charge storage and shallower junction regions at the source and drain interfaces. This segmentation allows the channel body to maintain charges more effectively by reducing leakage paths at the junction regions while preserving storage capacity in the deeper central region.
Solution Approach 2:
The invention transitions from a planar channel structure to a three-dimensional channel body with varying depth. The channel body extends deeper into the substrate at its center compared to the junction regions, creating a depth dimension that enhances charge storage capacity and retention by providing a larger volume for charge confinement away from leakage-prone interfaces.
2Duration of action of moving object
If the channel body volume is increased to improve charge storage capacity, then the retention time is elongated, but the device area increases
Solution Approach 1:
The cylindrical auxiliary gates are nested within trenches formed in the substrate, with the channel body formed between these nested cylindrical structures. This nested configuration allows the channel body to achieve increased effective volume for charge storage within a compact lateral footprint, improving retention time without proportionally increasing device area.
Solution Approach 2:
The channel body is formed with a curved, cylindrical geometry between the auxiliary gates rather than a straight planar configuration. This curved geometry increases the effective volume of the channel body within a given lateral space, enhancing charge storage capacity and retention time while maintaining a compact device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the volume of the channel body, reduces charge leakage through junction regions, and allows for a higher charge storage capacity, thereby elongating the data retention time and enabling efficient operation of capacitorless DRAM on a bulk substrate.
Implementation Method 1
a pair of cylindrical auxiliary gates connected with the plug nodes and contacting with each other within the substrate
Implementation Method 2
a substrate of a first conductivity type; source and drain regions of a second conductivity type
Data Source
AI summary
Provided are a capacitorless DRAM (dynamic random access memory) and a fabrication method thereof. In a capacitorless DRAM, a pair of cylindrical auxiliary gates is formed within a bulk substrate. Thus, a volume of a channel body formed at a region where the cylindrical auxiliary gates contact with each other can be increased, while an area of a junction region where the channel body contact source and drain regions can be reduced. As a result, capacitance of the channel body can be increased, and a generation of leakage current through the second junction region can be reduced. The application of a back bias to the cylindrical auxiliary gates can improve a charge storage capability of the channel body.