Cylindrical Channel Charge-Trapping Memory for Gate Coupling
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Solution Overview
Problem
Existing flash memory technologies face challenges in maintaining program/erase efficiency as device sizes shrink, particularly due to interference between neighboring floating gates and the inability to enhance electric field strength in dielectric charge trapping structures like SONOS cells.
Innovation Solution
A dielectric charge trapping memory cell design with a cylindrical channel surface and specific dielectric structure configurations that increase the electric field strength at the channel surface relative to the conductor surface, achieving a high 'effective' gate coupling ratio through carefully engineered area ratios and tunneling mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the area of the control gate and charge trapping structure is increased to improve coupling ratio, then the voltage coupled to the charge trapping structure increases, but this approach does not work for dielectric charge trapping structures because the series capacitor model does not apply
Solution Approach 1:
The patent applies curvature by forming the channel surface as a cylindrical structure instead of a planar surface. This curvature increases the electric field strength at the channel surface relative to the conductor surface, achieving a high effective gate coupling ratio without increasing the physical area of the control gate or charge trapping structure. The cylindrical geometry creates a non-uniform electric field distribution that concentrates the field at the channel interface, solving the problem of insufficient coupling in dielectric charge trapping structures.
2Power
If floating gate technology is used to achieve high coupling ratio through T-shape or U-shape gates, then program/erase efficiency is enhanced, but interference between neighboring floating gates occurs as device sizes shrink
Solution Approach 1:
The patent segments the charge storage function into separate components: a dielectric charge trapping structure isolated from both the channel and the control gate. This segmentation eliminates the interference problem between neighboring floating gates while maintaining the charge storage capability. The dielectric layer acts as an isolating barrier, preventing electrical interaction between adjacent memory cells while still allowing electric field coupling for programming and erasing operations.
Solution Approach 2:
The patent introduces a dielectric charge trapping structure as an intermediary between the control gate and the channel. This intermediary layer (such as silicon nitride or silicon oxynitride) mediates the charge storage function, allowing the control gate to influence the channel through electric field coupling without direct electrical connection. This intermediary structure eliminates the interference problem of floating gates while maintaining program/erase functionality through Fowler-Nordheim tunneling mechanisms.
3Reliability
If a dielectric charge trapping structure is used to eliminate floating gate interference, then neighboring gate interference is reduced, but the electric field strength in the tunneling dielectric is equal to that in the top dielectric, preventing coupling ratio enhancement
Solution Approach 1:
The patent uses cylindrical curvature of the channel surface to create a non-uniform electric field distribution. The curvature causes the electric field lines to concentrate at the channel surface interface with the tunneling dielectric, increasing the electric field strength in this region relative to the top dielectric layer. This geometric effect achieves coupling ratio enhancement without requiring area increases, solving the fundamental limitation of planar dielectric charge trapping structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances program/erase efficiency while suppressing unwanted charge leakage, improving performance beyond traditional floating gate and charge trapping technologies by optimizing electric field distribution.
Implementation Method 1
a cylindrical region of the channel surface... such that the ratio of the area A2 of the conductor surface to the area A1 of the channel surface is greater than or equal to 1.2... resulting in a higher 'effective' gate coupling ratio GCR
Implementation Method 2
a dielectric charge trapping structure is formed over a tunnel dielectric which isolates the dielectric charge trapping structure from the channel
Data Source
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AI summary
A vertical memory cell comprising: a source region and a drain region separated by a semiconductor channel region (200), the channel region having a channel surface (201) having an area A1 including a first cylindrical region, a first dielectric structure (202) on the channel surface (201), a dielectric charge trapping structure (203) on the first dielectric structure (202), a second dielectric structure (204) on the dielectric charge trapping structure (203), a conductive layer (205) having a conductor surface (206) having an area A2 including a second cylindrical region on the second dielectric structure (204), the conductor surface (206) overlying the dielectric charge trapping structure (203) and the channel surface (201) of the channel region (200), and the ratio of the area A2 to the area A1 being greater than or equal to 1.2 are described along with devices thereof and methods for manufacturing.