Cylindrical 1T-1C DRAM Layout for High Density and Low Leakage
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Solution Overview
Problem
Current dynamic random access memory (DRAM) technologies face challenges in achieving increased density and efficiency, particularly in scaling features of integrated circuits, which hinders computational performance and requires advancements in materials and device structures to reduce computation times.
Innovation Solution
The implementation of vertically aligned transistors with annular semiconductor structures and shared word lines, coupled with vertically aligned capacitors and shared capacitor plates, allows for a one transistor-one capacitor (1T-1C) DRAM architecture that enhances packing density and layout efficiency, especially when deployed at low temperatures, reducing leakage and improving carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional DRAM scaling is pursued, then computational efficiency improves, but manufacturing complexity and leakage increase
Solution Approach 1:
The patent transitions from planar 2D transistor structures to vertically aligned 3D cylindrical structures. The annular semiconductor structures and vertically extending word lines create a three-dimensional memory architecture that increases packing density without proportionally increasing manufacturing complexity, as the vertical alignment can be achieved through sequential deposition processes.
Solution Approach 2:
The memory structure is segmented into multiple vertically stacked layers including annular semiconductor structures, gate dielectric layers, and capacitor structures. This segmentation allows independent optimization of each layer and enables parallel processing during fabrication, reducing overall manufacturing complexity while maintaining high density.
2Quantity of substance
If feature size is reduced to increase density, then packing density improves, but leakage increases
Solution Approach 1:
The patent changes the geometric parameters of the transistor structure from planar to cylindrical, with vertically aligned word lines extending through annular semiconductor structures. This parameter change increases the effective channel length without increasing lateral footprint, improving density while the vertical configuration reduces leakage paths compared to scaled planar structures.
Solution Approach 2:
The structure employs nested concentric annular regions where inner annular structures are surrounded by outer annular structures. This nesting arrangement maximizes the use of available lateral space while maintaining vertical separation between memory cells, achieving high packing density without increasing leakage through proper isolation of adjacent cells.
3Quantity of substance
If capacitor size is reduced to increase density, then packing density improves, but carrier mobility decreases
Solution Approach 1:
The patent positions capacitors in the vertical dimension beneath the annular semiconductor structures, with capacitor plates extending vertically. This vertical placement frees up lateral space for denser transistor packing while the capacitor structures maintain sufficient volume for optimal electrical performance and carrier mobility through their vertical electrode configurations.
Data Source
AI summary
Integrated circuit dies, systems, and techniques are described herein related to one transistor-one capacitor dynamic random access memory. A memory device includes vertically aligned transistors having annular semiconductor structures and a shared bit line extending through the annular semiconductor structures, and vertically aligned capacitors having annular first capacitor plates, annular capacitor dielectric structures, and a shared second capacitor plate extending through the annular first capacitor plates, such that the annular first capacitor plates are in contact with corresponding ones of the annular semiconductor structures.