Cylindrical Ferroelectric Capacitor Layout for Dense DRAM Scaling
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Solution Overview
Problem
Scaling transistors for sub-10 nm nodes in DRAMs faces challenges due to reduced space for capacitors, increased variability, and leakage issues, limiting further scaling and memory density in conventional high-K dielectric materials.
Innovation Solution
The integration of ferroelectric materials with a cylindrical geometry and multiple outer electrodes allows for independent polarization control and reduced leakage, enabling efficient memory storage with enhanced scalability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-K dielectric materials are used for capacitors, then memory storage capacity can be maintained, but leakage increases and scaling to sub-10 nm nodes becomes limited
Solution Approach 1:
The patent changes the material parameter from conventional high-K dielectric to ferroelectric material, which fundamentally alters the electrical characteristics. This material substitution enables both leakage reduction through the ferroelectric switching mechanism and maintains scalability to sub-10 nm nodes by preserving capacitor functionality at reduced dimensions
Solution Approach 2:
The patent employs a composite structure combining ferroelectric material with metal electrodes (such as platinum, iridium, or ruthenium) to create a metal-ferroelectric-metal capacitor. This composite approach optimizes both the leakage characteristics through the ferroelectric layer and the electrical performance through the metal electrodes, enabling reliable scaling
2Productivity
If transistor size is reduced for sub-10 nm nodes, then memory density increases, but capacitor space is reduced and variability increases
Solution Approach 1:
The patent changes the capacitor material parameter to ferroelectric material, which has inherent non-volatile memory capability and reduced sensitivity to dimensional variations. This allows the capacitor to maintain stable performance even as the overall device size is reduced for sub-10 nm transistors, thereby supporting memory density increases without sacrificing reliability
Solution Approach 2:
The patent segments the capacitor structure into distinct functional layers (metal electrodes and ferroelectric material) that can be independently optimized. This segmentation allows the ferroelectric layer to provide stable polarization characteristics that are less sensitive to the reduced dimensions, while the metal electrodes provide robust electrical connections
3Reliability
If ferroelectric materials with cylindrical geometry and multiple outer electrodes are used, then leakage is reduced and polarization control is improved, but device complexity increases
Solution Approach 1:
The patent segments the capacitor into a cylindrical central electrode, a ferroelectric material layer, and multiple outer electrodes arranged circumferentially. This segmentation enables independent control of polarization in different spatial regions, achieving precise polarization control while the modular cylindrical design maintains fabrication simplicity
Solution Approach 2:
The patent transitions from a planar capacitor design to a three-dimensional cylindrical geometry with outer electrodes arranged in multiple angular positions. This dimensional change enables independent polarization control in different spatial regions without significantly increasing fabrication complexity, as the cylindrical structure can be formed using standard deposition and etching processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates the creation of densely packed, reliable memory storage bits with improved scalability and reduced leakage, leveraging the higher dielectric constant and domain-specific polarization of ferroelectric materials.
Implementation Method 1
a first spatial region in the ferroelectric layer between the first outer electrode and the second outer electrode corresponds to a first programmable bit and a second spatial region in the ferroelectric layer between the first outer electrode and the second outer electrode corresponds to a second programmable bit
Implementation Method 2
leveraging the higher dielectric constant and domain-specific polarization of ferroelectric materials
Data Source
AI summary
An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.