Cylindrical STT-MRAM Stack with Selective Insulating Cap
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Solution Overview
Problem
Current spin-transfer torque magnetoresistive random access memory (STT-MRAM) technologies face challenges in optimizing the structure and fabrication process to enhance write margin and chemical mechanical polishing (CMP) loading effects while maintaining lower power consumption and faster operating speeds.
Innovation Solution
The proposed magnetic memory device structure includes a substrate with distinct dielectric layers and via plugs, cylindrical memory stacks with magnetic tunnel junctions, and an insulating cap layer, along with specific spacer and interconnect configurations, allowing for improved electrical connections and CMP compatibility, and avoiding voids in the via forming region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional planar MTJ structure is used, then the fabrication process is simple, but the write margin is insufficient and power consumption is high
Solution Approach 1:
The patent employs a cylindrical MTJ structure instead of a conventional planar configuration. The cylindrical shape provides enhanced magnetic anisotropy and improved write margin through the perpendicular magnetization scheme, while the curved geometry naturally facilitates stress engineering for better TMR ratio without requiring additional complex layers
2Manufacturing precision
If multiple dielectric layers with different materials are used to optimize CMP performance, then CMP loading effects are improved, but the fabrication process complexity increases
Solution Approach 1:
The patent implements a multi-layer dielectric structure where each layer (first dielectric layer, second dielectric layer, and interlayer dielectric) has optimized material composition and thickness tailored to specific regional requirements. The first and second dielectric layers beneath the cylindrical MTJ are engineered with different properties than the interlayer dielectric to control CMP loading effects locally, allowing precise planarization control without uniform process complexity
Solution Approach 2:
The patent utilizes composite dielectric structures combining different materials (e.g., silicon oxide, silicon nitride, low-k materials) in specific layer configurations. These composite layers provide differentiated CMP response characteristics, enabling better loading effect management during chemical mechanical polishing while maintaining manufacturability through standard semiconductor fabrication processes
3Reliability
If the insulating cap layer is continuously disposed over the entire substrate including via forming regions, then electrical isolation is improved, but voids form during fabrication and cause shorting
Solution Approach 1:
The patent strategically removes the insulating cap layer from specific via forming regions where conductive vias need to be formed. This selective extraction allows via plugs to be formed directly to the underlying metal layers without the insulating cap layer interfering, preventing void formation and ensuring proper electrical connectivity, while the insulating cap layer remains in other regions to provide necessary electrical isolation
4Use of energy by moving object
If lower power consumption is achieved through optimized MTJ structure, then energy efficiency is improved, but operating speed may be reduced
Solution Approach 1:
The patent optimizes multiple parameters simultaneously including the thickness and composition of magnetic layers, the tunnel barrier thickness, and the cylindrical geometry dimensions. These parameter optimizations enable lower switching currents (reducing power consumption) while maintaining fast switching speeds through enhanced spin-polarized tunneling efficiency and reduced magnetic damping
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the write margin and CMP loading effects, ensuring efficient electrical connections and preventing shorting between conductive vias and memory stacks, thereby improving the overall performance and reliability of STT-MRAM devices.
Implementation Method 1
magnetic elements (MTJ elements) having MTJs utilizing a tunnel magneto resistance (TMR) effect
Implementation Method 2
spin-transfer torque magnetoresistive random access memory (STT-MRAM)
Data Source
AI summary
A magnetic memory device includes a first dielectric layer on a substrate, first and second via plugs in the first dielectric layer, first and second cylindrical memory stacks on the first and second via plugs, respectively, and an insulating cap layer conformally disposed on the first dielectric layer and on sidewalls of the first and second cylindrical memory stacks. The insulating cap layer is not disposed in a logic area and a via forming region between the first and second cylindrical memory stacks.