Cylindrical Nanotube FET for Electrostatic Control and Leakage Reduction
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Solution Overview
Problem
Conventional silicon-on-insulator (SOI)-based and ultra-thin body (UTB)-based multi-gate transistors face challenges in manufacturing due to high aspect ratio feature etching, cost, dopant diffusion, and uniform profile control, which complicates the scaling of transistor dimensions and increases device variability and leakage power dissipation.
Innovation Solution
A cylindrical-shaped nanotube field effect transistor (FET) architecture is introduced, featuring a ring-shaped second gate stack and a semiconductor material ring between the first and second gates, allowing for improved electrostatic control and reduced parasitic short channel effects through volume inversion, enabling higher drive current and reduced leakage without the need for complex doping profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI-based or UTB-based multi-gate transistors are used to improve electrostatic control and reduce short channel effects, then device performance is improved, but manufacturing complexity and cost increase due to high aspect ratio etching and dopant diffusion control
Solution Approach 1:
The patent employs a cylindrical gate structure surrounding the channel, replacing conventional planar or FinFET geometries. This cylindrical configuration provides 360-degree gate control over the channel, maximizing electrostatic control while maintaining manufacturability through standard semiconductor processing techniques.
Solution Approach 2:
The device structure nests the channel within a gate, which is in turn surrounded by contact regions. This nested configuration allows the gate to completely enclose the channel region, providing superior electrostatic control without requiring high aspect ratio etching or complex dopant implantation schemes.
2Area of stationary object
If transistor dimensions are scaled down to increase transistor density, then area is reduced allowing higher densities, but short channel effects and device variability increase
Solution Approach 1:
The cylindrical gate geometry provides uniform electrostatic control around the entire channel perimeter, even at scaled dimensions. This curvature-based structure maintains consistent electric field distribution regardless of channel length scaling, reducing variability while enabling higher density integration.
3Manufacturing precision
If conventional multi-gate devices are manufactured with high aspect ratio features, then better gate control is achieved, but manufacturing precision and uniform profile control become challenging
Solution Approach 1:
The cylindrical gate structure can be formed using standard circular etching and deposition processes, avoiding the need for high aspect ratio vertical structures. This curved geometry is more compatible with conventional manufacturing processes while delivering superior gate control.
Data Source
AI summary
A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (Ion/Ioff) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.