Cylindrical Read/Write Stacks for 3D Memory Leakage Control
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Solution Overview
Problem
Current flash memory systems face challenges in reducing the size and cost of memory cell arrays, particularly in efficiently accessing and programming large numbers of memory cells while minimizing leakage currents and parasitic currents, which affect performance and power consumption.
Innovation Solution
A three-dimensional memory array architecture with vertical bit lines and select devices, where memory elements are accessed through a framework of local and global bit lines, and word lines, allowing parallel access and reducing the need for diodes to manage leakage currents, utilizing materials like metal oxides and carbon for resistive switching elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional flash memory cell arrays are used, then data storage capacity is achieved, but leakage currents and parasitic currents increase, affecting performance and power consumption
Solution Approach 1:
The patent transitions from conventional two-dimensional memory cell arrays to a three-dimensional architecture with vertical bit lines extending through multiple planes. This dimensional change allows memory cells to be stacked vertically, increasing storage density while reducing the footprint and interconnect length, thereby minimizing leakage and parasitic currents associated with extended planar layouts.
Solution Approach 2:
The memory array is divided into multiple planes stacked vertically, with each plane containing a subset of memory cells. This segmentation allows independent addressing and operation of different planes, reducing the overall parasitic capacitance and leakage currents that would affect a monolithic two-dimensional array. The vertical bit lines serve multiple planes, reducing the total number of bit lines required.
2Ease of manufacture
If memory cell array size is reduced to lower cost, then manufacturing cost decreases, but access efficiency to large numbers of memory cells deteriorates
Solution Approach 1:
By stacking multiple planes vertically, the patent achieves higher storage capacity within a smaller footprint, effectively reducing the area required per memory cell. This three-dimensional arrangement maintains access efficiency because vertical bit lines provide direct access to cells across multiple planes, eliminating the need for extensive lateral interconnects that would increase area and cost.
Solution Approach 2:
The vertical bit lines serve multiple functions: they act as bit lines for selecting memory cells and simultaneously serve as word lines for programming operations. This multi-functionality reduces the total number of conductors required, simplifying the interconnect structure and reducing manufacturing complexity and cost while maintaining efficient access to all memory cells.
3Loss of energy
If diodes are added to manage leakage currents, then leakage control improves, but device complexity increases
Solution Approach 1:
The vertical bit line architecture inherently reduces leakage currents by minimizing the lateral extent of bit lines and reducing the number of bit line crossings with word lines. This geometric optimization reduces parasitic capacitance and leakage paths without requiring additional diode structures, thereby controlling leakage current while maintaining relatively simple device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture enhances data storage density, reduces manufacturing costs, and lowers operating voltages, while minimizing leakage currents and parasitic currents, enabling efficient parallel operations and improved reliability.
Implementation Method 1
The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them
Data Source
AI summary
A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material.