Cylindrical RRAM Cell Scaling Without Charge Pumps
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Solution Overview
Problem
Conventional RRAM devices face challenges in scaling down due to increasing forming voltages, which require significant charge pump circuitry, consuming space and limiting further miniaturization.
Innovation Solution
The RRAM material is formed around cylindrical conductive vias or posts, increasing the material area and eliminating the need for charge pumps, allowing for continued scaling by applying the forming voltage across the cylindrical structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If RRAM device dimensions are decreased for scaling, then device size is reduced, but forming voltage increases requiring charge pump circuitry that consumes space
Solution Approach 1:
The patent transitions from a planar RRAM structure to a three-dimensional cylindrical structure. The RRAM material is arranged in a cylindrical shape around a central via, with electrodes positioned at the top and bottom surfaces. This dimensional change increases the effective RRAM material area without increasing the planar footprint, thereby reducing the need for charge pump circuitry while maintaining compact device size.
Solution Approach 2:
The patent implements a nested structure where the RRAM material is positioned around a central conductive via, creating a concentric cylindrical arrangement. The bottom electrode is formed at the base of the via, the RRAM material wraps around the via sidewalls, and the top electrode caps the structure. This nesting approach maximizes the RRAM material area within a minimal planar footprint, eliminating the need for additional charge pump circuitry.
2Area of moving object
If RRAM device dimensions are decreased for scaling, then device size is reduced, but die space for charge pumps is increased
Solution Approach 1:
The patent transitions from a planar RRAM structure to a three-dimensional cylindrical structure. The RRAM material is arranged in a cylindrical shape around a central via, with electrodes positioned at the top and bottom surfaces. This dimensional change increases the effective RRAM material area without increasing the planar footprint, thereby reducing the need for charge pump circuitry while maintaining compact device size.
3Ease of manufacture
If conventional planar RRAM structure is used, then fabrication is simpler, but RRAM material area is limited
Solution Approach 1:
The patent implements a nested structure where the RRAM material is positioned around a central conductive via, creating a concentric cylindrical arrangement. The bottom electrode is formed at the base of the via, the RRAM material wraps around the via sidewalls, and the top electrode caps the structure. This nesting approach maximizes the RRAM material area within a minimal planar footprint, eliminating the need for additional charge pump circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient generation of high forming voltages without the need for charge pumps, enhancing memory cell scaling and array efficiency by increasing the RRAM material area, thus supporting next-generation memory performance.
Implementation Method 1
If the dielectric material is subjected to a high enough voltage, it will suddenly conduct because of dielectric breakdown. In a memristor, the dielectric breakdown is temporary and reversible because of the materials that are used.
Implementation Method 2
The controlled formation and destruction of filaments in large numbers allows for storage of digital data. The voltage that is used initially to cause the medium to acquire the microscopic conductive paths is called the forming voltage.
Data Source
AI summary
A memory cell is disclosed. The memory cell includes a word line contact, a cylindrical electrode having a top region and a bottom region, and RRAM material covering the surface of the cylindrical electrode from the top region to the bottom region. A select transistor contact is coupled to the bottom region of the cylindrical electrode.