Cylindrical Vertical Transistor MRAM Fabrication
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Solution Overview
Problem
Conventional MRAM storage density has reached a limit due to the constraints of developing smaller cells, and other random access memory technologies cannot match the storage density of MRAM.
Innovation Solution
The method involves forming cylindrical vertical transistors by creating a cylindrical pillar from a single block of silicon, forming an oxide layer, coating with spin-on-glass, and depositing a source mask to define a source contact recess, followed by ion-implanting and depositing a silicide material, which allows for increased drive currents and reduced footprint of MRAM cells by flowing operating current vertically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional MRAM cell size is decreased to increase storage density, then storage density is improved, but manufacturing precision and device reliability deteriorate due to reaching a size limit
Solution Approach 1:
The patent transitions from planar 2D MRAM cell architecture to a vertical 3D cylindrical architecture. The cylindrical pillar structure extends the channel in the vertical dimension, allowing current to flow vertically through the magnetoresistive stack rather than laterally. This dimensional change enables increased storage density without further reducing lateral cell footprint, as the vertical channel provides additional functional volume within the same planar area.
Solution Approach 2:
The patent inverts the conventional current flow direction in MRAM cells. Instead of horizontal current flow through planar channels, the cylindrical vertical transistor structure implements vertical current flow from the top surface through the pillar to the substrate. This inversion allows the magnetoresistive stack to be positioned vertically above the channel, enabling compact lateral footprint while maintaining functional performance.
2Ease of manufacture
If conventional planar transistor structure is used, then manufacturing process is simple, but drive current and performance are limited
Solution Approach 1:
The cylindrical vertical transistor structure utilizes the vertical dimension to increase channel length and cross-sectional area simultaneously. The circular cross-section of the pillar provides increased area for current flow compared to planar structures of equivalent lateral footprint. The vertical channel extends from the substrate through the pillar to the top surface, allowing longer channel length without increasing lateral dimensions, thereby improving drive current capability while maintaining compact area.
Solution Approach 2:
The cylindrical vertical transistor employs composite material structures including the cylindrical pillar formed from semiconductor material, oxide layer coating, spin-on-glass insulation layer, and silicide source contact. This composite structure combines materials with complementary properties to achieve both high drive current through the semiconductor channel and proper electrical isolation through the oxide and spin-on-glass layers, while the silicide contact provides low-resistance electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances the storage density and drive currents of MRAM devices, overcoming the limitations of conventional technologies by reducing the effective footprint of MRAM cells and improving performance.
Implementation Method 1
ion-implanting the exposed silicon substrate at a base of the source contact recess
Implementation Method 2
depositing a silicide material in the source contact recess, thereby forming a source contact
Data Source
AI summary
A method of forming a cylindrical vertical transistor; the method, according to one embodiment, includes: forming a cylindrical pillar from a single block of silicon, forming an oxide layer over an exterior of the cylindrical pillar and exposed surfaces of the block of silicon, coating the oxide layer with a spin-on-glass (SOG), depositing a source mask over a majority of the SOG coating, and removing a portion of the SOG coating and underlying oxide layer, where the portion removed is defined by the source mask. Other systems and methods are also described in additional embodiments herein which provide various different improved processes of forming the cylindrical gate contacts, the source contacts, and/or the drain contacts for vertical transistor structures which also include the aforementioned cylindrical pillar channel structures and cylindrical gate in comparison to conventional surface transistor structures.