Unified Cypher-Lock Field for Data Read Synchronization

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Solution Overview

Problem

Current data storage devices require multiple synchronization fields for data synchronization, which occupy space and are not compatible with asynchronous ADC sampling, necessitating a unified preamble field that can determine phase, gain, and start of data synchronization using asynchronous ADC samples.

Innovation Solution

A unified synchronization field, referred to as a cypher-lock field, is used, which encodes a phase modulated carrier signal to determine gain, phase, and start of data position using oversampled digital read signals, allowing for efficient data synchronization without the need for equalization or synchronization of the input signal from the ADC.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple synchronization fields are used for data synchronization, then synchronization accuracy is improved, but device complexity and space occupation increase

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidnumber of synchronization fields
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple separate synchronization fields (bit-sync field and word-sync field) into a single unified preamble field. This unified field contains both the bit synchronization pattern (e.g., repeated 2T or 3T pattern) and the word synchronization pattern (e.g., specific data pattern indicating start of data position), allowing the read channel to perform both bit synchronization and word synchronization from one consolidated structure, thereby reducing device complexity and space occupation while maintaining synchronization accuracy

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified preamble field serves multiple functions simultaneously: it provides bit synchronization for establishing gain and phase measurement values, provides word synchronization for determining start of data position, and occupies space efficiently. This multi-functional design eliminates the need for separate synchronization fields while achieving all necessary synchronization objectives

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If traditional synchronization fields are used, then synchronization function is provided, but compatibility with asynchronous ADC sampling is poor

Engineering Contradiction:
Improvecompatibility with asynchronous ADC samplingVSAvoidsynchronization performance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent changes the parameter of the synchronization field from traditional separate bit-sync and word-sync fields to a unified preamble field with specific structural parameters. The unified field uses a predetermined pattern structure that allows correlation-based detection to work effectively with asynchronous ADC samples, enabling the system to determine both bit synchronization and word synchronization positions from the same sampled data without requiring separate synchronization fields

Inventive Principle:
Principle #35Parameter changes

3Loss of information

If separate bit-sync and word-sync fields are used, then synchronization completeness is improved, but manufacturing cost and processing complexity increase

Engineering Contradiction:
Improvesynchronization completenessVSAvoidmanufacturing cost and processing complexity
Core Design Contradiction:
Loss of informationVSEase of manufacture

Solution Approach 1:

The patent merges separate bit-sync and word-sync fields into a single unified preamble field that contains all necessary synchronization information. The unified field structure allows the read channel to extract both bit synchronization parameters (gain, phase) and word synchronization position (start of data) from the same data structure, reducing manufacturing complexity and processing overhead while maintaining complete synchronization functionality

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified preamble field performs multiple synchronization functions simultaneously - bit synchronization for gain and phase measurement, and word synchronization for start of data position determination. This universal synchronization structure eliminates the need for separate processing paths for different synchronization types, simplifying manufacturing and reducing processing complexity while ensuring synchronization completeness

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution improves manufacturing costs, timing performance, and error rates by enabling more efficient data synchronization from asynchronous ADC signals, making data storage devices more reliable and cost-effective.

Implementation Method 1

A read element 214 may be configured to detect magnetized portions of magnetic surface 206 and generate an analog read signal

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Implementation Method 2

A unified synchronization field, referred to as a cypher-lock field, is used, which encodes a phase modulated carrier signal

Methodology Applied
Scientific EffectPhase modulation: Phase Modulation

Data Source

PatentUS12183376B1Data read synchronization from phase modulated synchronization fields in a data storage device
Publication Date: 2024.12.31 WESTERN DIGITAL TECHNOLOGIES INC
  • US12183376B1 patent drawing
  • US12183376B1 patent drawing
  • US12183376B1 patent drawing

AI summary

Example channel circuits, data storage devices, and methods for data read synchronization from phase modulated synchronization fields are described. A data synchronization detector may receive an oversampled digital read signal read from a synchronization field that uses a single written pattern to encode the start of data position, phase, and gain for the read channel. The write pattern may use a phase modulated carrier signal to encode a pseudo-random binary sequence indicating the start of data position.