Multi-bit D Flip-Flop Soft Error Tolerant Circuit
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Solution Overview
Problem
Current circuit designs fail to provide robust protection against both Single Event Upsets (SEUs) and Single Event Transients (SETs) while maintaining high performance and low cost, often sacrificing cost and performance for robustness against radiation-induced failures.
Innovation Solution
A logic circuit with dual sets of storage elements sampling data at different clock signals, utilizing parity generators and an error correction unit that compares time-delayed parity checks to detect and correct errors, allowing for adjustable timing and operational adjustments based on error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TMR designs are used to improve tolerance against SEUs, then reliability is improved, but cost and power requirements increase significantly
Solution Approach 1:
The circuit is divided into two distinct sets of storage elements (first set and second set) that operate independently with different clock signals. This segmentation allows each set to be optimized for specific error detection purposes, achieving comprehensive SEU and SET tolerance without requiring the full redundancy of TMR designs, thereby reducing cost and power requirements.
Solution Approach 2:
The first parity generator creates a preliminary parity check of the data inputs before they are clocked into the storage elements. This preliminary parity check is then delayed and compared with the second parity check generated after clocking, enabling proactive error detection before errors propagate through the system, thus improving reliability without full TMR redundancy.
2Reliability
If TMR designs are implemented to protect against radiation strikes, then reliability is improved, but performance is limited compared to other configurations
Solution Approach 1:
The circuit uses periodic clock signals with different phases to sample data into the first and second sets of storage elements. This periodic sampling allows the error correction unit to compare parity checks at different time instances, detecting both SEUs (single-time errors) and SETs (transient errors), thereby maintaining high performance while achieving comprehensive radiation protection.
Solution Approach 2:
The error correction unit receives feedback from comparing the delayed first parity check with the second parity check. Based on this feedback, the circuit can identify and correct errors, ensuring reliable operation under radiation conditions without the performance penalties associated with TMR designs.
3Reliability
If existing robust circuit designs are used to protect against both SEUs and SETs, then reliability is improved, but cost and performance are sacrificed
Solution Approach 1:
The dual set of storage elements serves multiple functions: the first set captures data for preliminary parity checking, the second set captures data for final parity checking, and both sets enable detection of different error types (SEUs and SETs). This multi-functionality achieves comprehensive error protection without requiring separate dedicated circuits for each error type, thereby reducing overall device complexity and cost.
Solution Approach 2:
The delay unit acts as an intermediary between the first parity generator and the error correction unit. It temporarily holds the first parity check and synchronizes it with the second parity check timing, enabling accurate comparison without requiring complex timing control logic, thus simplifying the overall circuit design while maintaining robust error detection capabilities.
Data Source
AI summary
A circuit and methods of operation thereof are provided for robust protection against soft errors. The circuit includes a first set of storage elements coupled to and configured to sample a set of data inputs at a first set of times. The circuit includes a second set of storage elements coupled to and configured to sample the set of data inputs at a second set of times. A first parity generator generates a first parity check for the set of data inputs and a second parity generator generates a second parity check for output of the first set of storage elements. An error correction unit compares the first parity check and the second parity check to detect occurrences of error conditions in the circuit. The error correction unit may control output or operating characteristics of the circuit as a result of error conditions detected.