Radiation-Hardened D Flip-Flop With SET Glitch Filtering
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Solution Overview
Problem
Conventional flip-flop circuits are vulnerable to single-event upsets due to radiation, requiring additional circuits and space for sensitivity node separation, which is not feasible for compact implementations in aircraft and spacecraft, and increases power consumption and silicon area.
Innovation Solution
A radiation-hardened D flip-flop circuit incorporating first and second dual-input inverters, single and dual-input tri-state inverters, and single-event transient (SET) filters, with temporal filters to reject glitches and minimize area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuits and space are added for sensitive nodes separation in conventional flip-flop circuits, then radiation hardness is improved, but silicon area and power consumption increase significantly
Solution Approach 1:
The circuit is divided into two separate paths (first path and second path) within the dual-input inverter structure. Each path processes signals independently through separate transistors and SET filters, allowing the circuit to reject single-event transients while maintaining compact area. The segmentation of signal paths enables radiation hardness without requiring large spacing between sensitive nodes.
Solution Approach 2:
SET filters are introduced as intermediary elements between the input signals and the inverter inputs. These filters act as mediators that condition the signals and block single-event transients before they reach the sensitive inverter nodes. The SET filters include delay elements and logic gates that process and clean the signals, providing radiation hardening without requiring extensive physical separation of sensitive nodes.
2Reliability
If additional circuits and space are added for sensitive nodes separation in conventional flip-flop circuits, then radiation hardness is improved, but power consumption increases
Solution Approach 1:
The circuit segments the signal processing into two parallel paths with shared resources. Each path has its own transistors and filter elements, but the overall structure reuses the dual-input inverter and clocking mechanisms. This segmentation provides radiation hardness through path diversity while controlling power consumption by avoiding complete duplication of all circuit elements.
Solution Approach 2:
The dual-input inverter structure serves multiple functions: it processes signals from two different paths, provides clocking control through shared clock inputs, and generates the output signal. The SET filters also serve dual purposes of signal conditioning and transient rejection. This multi-functionality reduces the need for additional dedicated circuits, thereby controlling power consumption while maintaining radiation hardness.
3Reliability
If temporal filters are added to reject glitches, then radiation hardness is improved, but device complexity increases
Solution Approach 1:
SET filters are positioned as intermediary elements between the input signals and the inverter inputs. Each SET filter includes a delay element and logic gates that work together to detect and reject single-event transients. The filters process signals through a standardized structure that, while adding some complexity, provides a systematic and manageable approach to radiation hardening rather than requiring complex redundant circuitry throughout the entire flip-flop.
Data Source
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AI summary
A flip-flop circuit is disclosed. The flip-flop circuit includes a single-input inverter, a dual -input inverter, a single-input tri-state inverter, a dual -input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the flip-flop circuit.