Soft-Error-Tolerant D Flip-Flop With Minimal Transistor Overhead
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Solution Overview
Problem
Conventional D-type flip-flop circuits face increased circuit area and delay time when enhanced for soft error tolerance, making them unsuitable for high-frequency clock systems.
Innovation Solution
A D-type flip-flop circuit design that adds only two MOS transistors to the general D-type flip-flop circuit, incorporating a tri-state inverter with additional pMOS and nMOS transistors to enhance soft error tolerance without increasing circuit area or delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TMRFF (Triple Modular Redundancy Flip Flop) is used to enhance soft error tolerance, then reliability is improved, but circuit area increases to about 5.2 times
Solution Approach 1:
Instead of implementing full triple modular redundancy (100% redundancy), the patent applies a partial redundancy approach by adding only one additional transistor to the conventional flip-flop structure. This provides enhanced soft error tolerance through selective reinforcement of critical nodes without the complete triplication of the entire circuit, achieving improved reliability with minimal area overhead.
2Reliability
If TMRFF is used to enhance soft error tolerance, then reliability is improved, but delay time increases to about 1.5 times
Solution Approach 1:
The patent implements partial redundancy by reinforcing only the critical latch nodes with additional transistors rather than triplicating the entire signal path. This selective approach maintains the original clock-to-Q delay characteristics while providing soft error tolerance at vulnerable points, avoiding the cumulative delay penalty of full TMR architecture.
3Reliability
If TMRFF is used to enhance soft error tolerance, then reliability is improved, but power consumption increases to about 3.2 times
Solution Approach 1:
The patent employs partial redundancy by adding minimal transistor components only where soft error vulnerability is highest, rather than activating three times the original power-consuming elements. This results in negligible increase in dynamic power consumption while achieving the desired reliability improvement through targeted protection.
4Reliability
If conventional D-type flip-flop circuit is enhanced for soft error tolerance, then soft error tolerance is improved, but circuit area increases
Solution Approach 1:
The patent merges the soft error protection function with the existing flip-flop structure by integrating additional transistors into the conventional latch circuit topology. The protective transistors are combined with the existing pull-up and pull-down networks, sharing common nodes and pathways, thereby achieving soft error tolerance without proportional area increase.
Solution Approach 2:
The additional transistors in the patent serve multiple functions simultaneously: they provide soft error tolerance through node reinforcement, maintain the original flip-flop logic functionality, and integrate with the existing clocking and data transmission pathways. This multi-functionality eliminates the need for separate protection circuits, minimizing area overhead.
Data Source
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AI summary
A D-type flip-flop circuit 1 has a structure in which a pMOS transistor p8 and an nMOS transistor n8 are added to a general D-type flip-flop circuit comprising pMOS transistors p1 to p7, p11 to p15 and nMOS transistors n1 to n7, n11 to n15.