Image Sensor Counter Circuit with D-Latch for Noise-Stable Conversion

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Solution Overview

Problem

Existing image sensors face challenges in reducing noise and coupling influences during the conversion of analog signals to digital signals, particularly in high-definition imaging, due to fluctuations in complement control signals affecting the accuracy of complement operations.

Innovation Solution

Incorporating a counter with a division function and a D-latch to perform stable complement and division operations, which reduces the impact of coupling and enables effective reset multiple sampling techniques, thereby enhancing noise reduction and image reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a counter is used to convert analog signals to digital signals in high-definition image sensors, then the conversion capability is improved, but noise and coupling influences increase due to fluctuations in complement control signals

Engineering Contradiction:
Improvesignal conversion accuracyVSAvoidnoise and coupling influences
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a D-latch as an intermediary component between the complement control signal and the counter. The D-latch stabilizes the complement control signal by latching it during the counting operation, preventing fluctuations from directly affecting the counter. This intermediary element isolates the counter from harmful signal variations, reducing noise and coupling influences while maintaining accurate analog-to-digital conversion capability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If complement operations are performed during analog-to-digital conversion, then the digital signal accuracy is improved, but the system becomes sensitive to fluctuations in complement control signals

Engineering Contradiction:
Improvedigital signal accuracyVSAvoidcomplement control signal stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by stabilizing the complement control signal before it is used in the complement operation. The D-latch captures and holds the complement control signal at a stable state prior to the counting operation, ensuring that the signal does not fluctuate during the critical complement operation. This preliminary stabilization ensures reliable digital signal accuracy while maintaining system stability

Inventive Principle:
Principle #10Preliminary action

3Object-affected harmful factors

If reset multiple sampling techniques are applied to reduce noise, then the image quality is improved, but the complexity of the counter circuit increases

Engineering Contradiction:
Improvenoise levelVSAvoidcounter circuit complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The D-latch serves as a simple intermediary that enables reset multiple sampling techniques without significantly increasing circuit complexity. By providing a stable complement control signal through the latch, the system can perform multiple sampling operations to reduce noise. The D-latch adds minimal complexity compared to the benefits gained from noise reduction through multiple sampling

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3809695B1Counter circuit and image sensor including the same
Publication Date: 2022.12.21 SAMSUNG ELECTRONICS CO LTD
  • EP3809695B1 patent drawingFigure 1
  • EP3809695B1 patent drawingFigure 2
  • EP3809695B1 patent drawingFigure 3

AI summary

An image sensor includes a pixel sensor configured to sense an incident light and to output an analog sampling signal; a sampling unit comparing the sampling signal and a ramp signal, and outputting a comparison signal having a duration that is indicative of the amplitude of the sampling signal; and a counter counting a length of the comparison signal based on a clock signal and first and second complement control signals. The counter includes an AND gate ANDing the comparison signal and the clock signal; and a counting unit triggered at a falling edge of the AND gate output to output a count value. The counting unit includes a complement operation controller storing an inverted count value that is an inversion of the count value in response to the first complement control signal, and outputting the inverted count value in response to the second complement control signal; and a D-flip-flop that is set or reset depending on the inverted count value, and outputs the count value.