D-mode FET Driver Startup Sequence Reliability

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Solution Overview

Problem

Existing half-bridge driver designs using D-mode power FETs face challenges during startup, particularly in avoiding output voltage overload and damaging uncontrolled charging currents that can affect gate-source junctions, due to the need for a sufficiently high negative voltage to reliably turn off the FETs.

Innovation Solution

The proposed solution involves an electronic circuit with a voltage monitor to ensure the DC voltage is below a threshold before initiating dummy cycles, and the use of switchable current sources or negative power supply circuits to charge coupling capacitors safely, preventing overvoltage and damage to the FETs and connected circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dummy cycles are initiated during startup to charge coupling capacitors, then power FETs can be reliably turned off, but uncontrolled charging currents may damage gate-source junctions

Engineering Contradiction:

Improvereliable FET turn-offVSAvoiduncontrolled charging current damage

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The voltage monitor circuit checks the DC voltage level before initiating dummy cycles to charge coupling capacitors. This preliminary verification ensures that charging only occurs when voltage conditions are safe, preventing uncontrolled charging currents from damaging gate-source junctions while still achieving reliable FET turn-off.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

A voltage monitor circuit acts as an intermediary between the power supply and the dummy cycle initiation. This intermediary monitors DC voltage levels and controls when charging of coupling capacitors occurs, mediating between the need to charge capacitors for reliable FET turn-off and the risk of damaging currents.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If dummy cycles are used to charge coupling capacitors, then FETs can be reliably turned off, but output voltage overload may occur

Engineering Contradiction:

Improvereliable FET turn-offVSAvoidoutput voltage overload

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The voltage monitor provides feedback on DC voltage levels to control the initiation of dummy cycles. This feedback mechanism ensures that charging of coupling capacitors only occurs when voltage conditions are appropriate, preventing output voltage overload while achieving reliable FET turn-off.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system performs a preliminary voltage check before initiating dummy cycles. This preliminary action verifies that DC voltage is within safe limits, preventing output voltage overload during capacitor charging while ensuring reliable FET turn-off.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If switch FET is kept OFF during startup to prevent short circuits, then safety is improved, but circuit productivity is reduced

Engineering Contradiction:

Improveshort circuit preventionVSAvoidcircuit startup speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The voltage monitor performs a preliminary check of DC voltage levels before enabling dummy cycles. This preliminary action allows the circuit to quickly determine safe operating conditions, reducing startup delay while maintaining short circuit prevention by keeping the switch FET OFF until voltage conditions are verified.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The voltage monitor circuit automatically detects when DC voltage is within safe limits and enables dummy cycles without external intervention. This self-service mechanism reduces startup time by eliminating manual verification steps while maintaining safety through automatic voltage monitoring.

Inventive Principle:

Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures that power FETs are reliably turned off during startup, preventing output voltage overload and damage to gate-source junctions, while allowing for faster and safer charging of capacitors, thereby protecting voltage-sensitive circuits.

Implementation Method 1

dummy cycles to charge coupling capacitors (C1, C2) that are respectively inserted between their corresponding drivers (DRV1, DRV2) and power FETs (T1, T2)

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

a voltage monitor to ensure the DC voltage is below a threshold before initiating dummy cycles

Methodology Applied

Scientific EffectVoltage detection:

Implementation Method 3

the use of switchable current sources or negative power supply circuits to charge coupling capacitors safely

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS11057031B1Reliability in start up sequence for D-mode power FET driver

Publication Date: 2021.07.06 MURATA MFG CO LTD

AI summary

Methods and devices to address start up of half-bridge circuits including D-mode power FETs are disclosed. The disclosed devices overcome possible issues of output overload or excess current through gate-source of power FETs during start up. Methods and devices based on monitoring coupling capacitors voltages and pre-charging such coupling capacitors using current sources are also described. The current sources can be implemented using negative voltages provided by negative voltage sources such as charge pumps.