D-PHY Deskew Circuit Using Sampling-Based Phase Calibration
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Solution Overview
Problem
The high system complexity and cost of implementing phase calibration in D-PHY deskew technology due to the use of multi-phase clocks and phase-locked loops necessitate a simplified circuit composition for phase calibration.
Innovation Solution
A circuitry and method involving a receiving data lane, clock signal lane, deskew control module, and deskew module to sample data signals, determine delay information, and adjust phase offsets, simplifying the circuitry by using a deskew control module to phase offset clock and data signals based on determined delay information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-phase clocks and phase-locked loops are used to achieve phase calibration in D-PHY deskew technology, then phase calibration accuracy is improved, but system complexity and implementation cost increase
Solution Approach 1:
The patent extracts and eliminates the complex phase-locked loop circuitry and multi-phase clock generation components from the deskew system. Instead of using these traditional high-precision but high-complexity components, the invention employs a simplified approach using a single clock signal and a deskew control module that processes timing information through sampling and delay determination, thereby reducing circuit complexity while maintaining calibration functionality
Solution Approach 2:
The patent replaces the traditional mechanical/electrical phase-locked loop system with a digital signal processing approach. The deskew control module uses digital sampling of data signals, digital delay determination based on sampled data, and digital phase offset adjustment, substituting the analog/physical phase calibration mechanism with a digital processing system that achieves similar functionality with reduced hardware complexity
Data Source
AI summary
A circuitry, method, computer storage medium, and terminal for deskew processing include: receiving data lanes, clock signal lanes, deskew control modules, and deskew modules. The receiving data lane receives input data signals, which are in alternating standard sequence. The clock signal lane receives input clock signals. The deskew control module is connected to the receiving data lane and is set to acquire the sample data obtained by sampling the data signal of the data signal lane by the clock signal of the clock signal lane with a preset duration, and determine the delay information based on the sample data. The deskew module is connected to the deskew control module and is set to adjust the phase offset of both the clock signal and the data signal based on the delay information. The embodiments of the present invention sample the data signal and determine the delay information by the deskew control module, adjust the phase offset by the delay information, simplifying the circuitry composition of phase calibration.