D2D Interconnect Test Circuit With Dual-Frequency Scan and Capture
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Solution Overview
Problem
Existing multi-die integrated circuits face challenges in effectively testing Die-to-Die (D2D) interconnects due to the need for accurate delay testing under functional frequency conditions without causing errors or missed control data transmission.
Innovation Solution
A two-stage testing approach is employed, using a lower frequency for control data transmission and a higher frequency for test data transmission, with source synchronous clocking to mitigate timing issues and ensure accurate D2D interconnect testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single high frequency is used for both control data and test data transmission, then the delay test speed is improved, but control data transmission errors increase
Solution Approach 1:
The patent segments the transmission process into two distinct stages: a first operation stage for control data transmission at a lower frequency, and a second operation stage for test data transmission at a higher frequency. This segmentation allows each stage to operate at the optimal frequency for its specific function, resolving the contradiction between test speed and control data accuracy.
Solution Approach 2:
The patent dynamically adjusts the operating frequency based on the transmission stage. The interface circuits switch between a lower frequency during control data transmission and a higher frequency during test data transmission. This dynamic frequency adjustment enables the system to maintain reliability during control operations while achieving high-speed testing during data transmission.
2Reliability
If a single low frequency is used for both control data and test data transmission, then control data transmission accuracy is improved, but the delay test speed decreases
Solution Approach 1:
The patent divides the transmission process into two separate operation stages with different frequency requirements. The first stage uses a lower frequency for reliable control data transmission, while the second stage uses a higher frequency for accelerated test data transmission. This segmentation resolves the contradiction by allowing each stage to operate at its optimal frequency.
Solution Approach 2:
The patent implements periodic switching between two frequency modes. During the first operation stage, the system operates at a lower frequency for control data; during the second operation stage, it switches to a higher frequency for test data. This periodic frequency switching enables the system to achieve both high reliability and high productivity throughout the testing process.
3Measurement precision
If the test frequency is increased to match functional frequency, then the accuracy of D2D interconnect performance reflection is improved, but timing issues and data transmission errors increase
Solution Approach 1:
The patent segments the operational frequencies into two distinct levels: a lower first frequency for control data transmission that ensures reliability, and a higher second frequency matching the functional frequency for test data transmission that ensures measurement accuracy. This segmentation allows the system to achieve accurate D2D interconnect performance reflection without compromising data transmission reliability.
Solution Approach 2:
The patent dynamically adjusts the operating frequency based on the operational stage and data type. The interface circuits switch between a lower frequency during control operations and a higher functional-matching frequency during test operations. This dynamic frequency adaptation enables the system to maintain both reliability and measurement precision.
Data Source
AI summary
A circuit includes a first die including first and second interface circuits, a second die including third and fourth interface circuits, and a first interconnect configured to operatively couple the first die through the first and second interface circuits to the second die through the third and fourth interface circuits. During a first operation stage, the first interface circuit to the fourth interface circuit are each configured to receive control data based on a first frequency, the control data including a series of scan data bits for testing the first interconnect. During a second operation stage following the first operation stage, the first interface circuit to the fourth interface circuit are each configured to receive test data based on a second frequency, the test data including a series of capture data bits for testing the first interconnect. The second frequency is substantially higher than the first frequency.