Die-to-Die Interconnect Traffic Channel Distribution
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Solution Overview
Problem
The increasing complexity and cost of processing data in central locations, such as monolithic system-on-chip (SoC), due to the generation of more data by devices, necessitates a solution for efficiently transmitting multiple traffic channels across die-to-die interconnects with different protocols, which existing technologies have not adequately addressed.
Innovation Solution
A die-to-die interconnect architecture that includes transmit and receive selection circuits, gearboxes, and physical layer interfaces, configured to handle multiple traffic channels with different protocols, allowing for efficient data streaming and error correction, prioritization, and resource sharing to optimize bandwidth and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple traffic channels with different protocols are transmitted across die-to-die interconnects, then bandwidth and resource utilization are improved, but device complexity and protocol compatibility become problematic
Solution Approach 1:
The patent introduces protocol translation circuits and conversion interfaces as intermediary components between different protocol domains. These intermediaries translate between proprietary interconnect protocols and standard protocols (PCIe, CXL, NVLink), enabling heterogeneous protocol communication without requiring end systems to support all protocols directly.
Solution Approach 2:
The interconnect architecture implements universal interface circuits that can handle multiple protocol types simultaneously. The conversion interface is designed to support various protocols (PCIe, CXL, NVLink, proprietary) through a unified structure, allowing a single interconnect to serve multiple protocol families without requiring separate dedicated paths for each protocol.
2Productivity
If data is processed in central locations such as monolithic SoC, then processing capability is improved, but cost and complexity of processing increase
Solution Approach 1:
The patent applies segmentation by dividing the monolithic SoC into multiple independent component dies (chiplets), each performing specific processing functions. These segmented units can be independently manufactured, tested, and assembled, reducing overall system complexity while maintaining or enhancing processing capability through parallel operation.
Solution Approach 2:
The patent transitions from a two-dimensional planar interconnect architecture to a three-dimensional stacked architecture. By stacking component dies vertically and using through-silicon vias for interconnection, the system achieves higher processing density and bandwidth without proportionally increasing lateral footprint or complexity.
3Adaptability or versatility
If disaggregated SoC with multiple component dies is used, then modularity and flexibility are improved, but interconnect bandwidth and latency become critical
Solution Approach 1:
The patent employs three-dimensional stacking of component dies with vertical interconnects through the substrate. This vertical arrangement reduces the physical distance data must travel between component dies compared to lateral arrangements, thereby reducing latency while maintaining modularity.
Solution Approach 2:
The interconnect architecture pre-establishes multiple high-bandwidth communication channels between component dies during assembly. Protocol translation capabilities are pre-configured in the interconnect circuits, allowing rapid protocol conversion without adding latency during runtime communication.
Data Source
AI summary
Disclosed is die-to-die (D2D) interconnect of a component die. In an aspect, the D2D interconnect includes a transmit selection circuit, a plurality of transmit gearboxes (Tx GBXs), and a plurality of transmit D2D physical layer interfaces. The transmit selection circuit may be configured to receive at least two traffic channels and to output a data stream of at least one traffic channel to the plurality of Tx GBXs. Each of a subset of Tx GBXs may be configured to receive at least a portion of the data stream from the transmit selection circuit and to output at least the portion of the data stream to a transmit D2D physical layer interface to which the Tx GBX is communicatively coupled. Each transmit D2D physical layer interface coupled to the subset of Tx GBXs may be configured to output at least the portion of the data stream.