D2D Interconnect Lane Mapping for Chiplet Pin Mismatch
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Solution Overview
Problem
Existing systems face challenges in efficiently configuring die-to-die (D2D) interconnects in chiplet architectures, particularly in managing pin mismatch and latency issues when implementing high-capacity and high-speed memory solutions.
Innovation Solution
The implementation of Universal Chiplet Interconnect express (UCIe) protocol and mapping tables to manage the correlation between the number of connected chiplet dies and signal pins, allowing for flexible allocation of pins based on capacity or performance requirements, and the use of redundant lanes for handling defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If pin allocation is fixed in traditional memory interfaces, then manufacturing simplicity is maintained, but adaptability to different chiplet configurations is reduced
Solution Approach 1:
The patent implements dynamic pin allocation where the pin assignment is not fixed but can be reconfigured based on the number and type of chiplet dies connected. The system determines optimal pin allocation dynamically during system initialization or configuration phase, allowing the same physical interface to adapt to different memory capacities and performance requirements without hardware changes.
Solution Approach 2:
The system changes operational parameters (pin assignments, lane configurations) based on detected chiplet configurations. By varying pin allocation parameters according to the number of chiplet dies and their capabilities, the system achieves adaptability while managing complexity through parameterized control rather than structural changes.
2Quantity of substance
If more signal pins are allocated to increase memory capacity, then storage capacity is improved, but latency increases due to additional routing paths
Solution Approach 1:
The patent segments the memory interface into multiple independent lanes, each capable of operating autonomously. By dividing the data path into separate lanes that can be independently configured and activated, the system increases total memory capacity through parallelism while maintaining low latency within each lane. Each lane processes data independently, avoiding the latency penalty of sequential routing through a single expanded interface.
Solution Approach 2:
The system transitions from increasing capacity through wider single-path routing (which increases latency) to increasing capacity through additional parallel dimensions (multiple lanes). By adding temporal and spatial parallelism across multiple independent lanes rather than expanding a single data path, the system achieves higher capacity without proportionally increasing access latency.
3Reliability
If redundant lanes are implemented to handle defects, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements lanes that serve multiple functions: they can be actively used for data transmission, placed in standby for redundancy, or configured as spares for defect replacement. The same physical lane infrastructure supports normal operation, redundancy, and fault tolerance without requiring separate dedicated structures, achieving reliability improvement while limiting complexity growth through multi-functional design.
Solution Approach 2:
The system incorporates automated defect detection and lane replacement capabilities that operate without external intervention. When defects are detected in active lanes, the system automatically switches to redundant lanes or reconfigures the interconnect to bypass defective paths, providing self-healing functionality that improves reliability while managing complexity through automated control rather than manual configuration.
Data Source
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AI summary
An apparatus includes a first die connected to a second die through a die-to-die (D2D) interface. The first die (memory controller) includes a first interconnect configured to provide first lanes communicating with the second die to the D2D interface, the first interconnect includes a first logic circuit configured to indicate a correlation between a number of chiplet dies connected to the first lanes and connected signal pins of each connected chiplet dies. The second die includes the number of connected chiplet (memory chiplet) dies each including a correspondiong second interconnect configured to provide corresponding second lanes to the D2D interface from each of the connected chiplet dies. The second lanes of the connected chiplet dies are configured to be set according to a number of the connected signal pins of the connected chiplet dies.