D2D Transceiver Clocking for Flexible Multi-Die Data Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor die designs for high-performance systems-on-chip (SoC) face challenges in transmitting large-scale data at high speeds due to limited computing capability and bandwidth, and the manufacturing of large dies results in decreased yield, with existing reference clock designs only supporting basic requirements for single scenarios and lacking flexibility for multi-application scenarios.
Innovation Solution
The semiconductor die incorporates a D2D transceiver with phase locked loops to provide high-quality reference clock signals for data transmission within and between dies, supporting multiple application scenarios by using differential CML clock signals and multiple transceivers to ensure reliable and flexible data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large scale high performance SoC is manufactured to transmit large scale data at high speed, then computing capability and bandwidth are improved, but manufacturing yield decreases
Solution Approach 1:
The patent divides the large scale SoC into multiple smaller semiconductor dies, each with its own reference clock source. This segmentation allows each die to be manufactured independently with higher yield, while collectively achieving the required data transmission capacity through parallel operation of multiple dies.
Solution Approach 2:
The patent transitions from a single-die architecture to a multi-die three-dimensional stacked architecture, enabling data transmission across different spatial dimensions. This allows high bandwidth communication between dies through vertical interconnects while maintaining individual die sizes that preserve manufacturing yield.
2Adaptability or versatility
If reference clock design supports only single scenario (die PCIE or host), then basic requirements are met, but multi-application scenarios cannot be flexibly configured
Solution Approach 1:
Each semiconductor die is equipped with its own reference clock source and phase locked loop circuitry, making each die self-sufficient and capable of operating independently in various scenarios. This universal design allows the same die architecture to support D2D communication, PCIE interfaces, host connections, and hybrid configurations without requiring complex external clock distribution networks.
Solution Approach 2:
Each die generates and manages its own reference clock signals through on-chip phase locked loops, eliminating the need for complex external clock distribution systems. This self-service approach simplifies the overall system design while enabling flexible configuration for different application scenarios, as each die can independently adjust its clocking according to its specific communication needs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-speed, reliable data transmission between semiconductor dies, improving manufacturing yield and supporting various application scenarios with reduced signal jitter and increased robustness by using differential CML clock signals and phase locked loops.
Implementation Method 1
a first phase locked loop, configured to receive an initial reference clock signal from outside the semiconductor die, and to provide the first reference clock signal to the first D2D transmitter
Implementation Method 2
The single end CMOS clock signal is converted into a differential CML clock signal via a phase locked loop
Data Source
AI summary
A semiconductor die is provided. The semiconductor die includes a D2D transceiver composed of a single die or dual dies. The D2D transceiver includes a first D2D transmitter and a first D2D receiver. The D2D transmitter is configured to send data to a second D2D receiver in a second D2D transceiver of another semiconductor die using a first reference clock signal. The D2D receiver is configured to receive data from a second D2D transmitter in the second D2D transceiver using a second reference clock signal. Through using the embodiments of the disclosure, a transmission solution may be flexibly configured for a multi-application scenario including D2D.