D2D Valid Signaling for Low-Latency Error Framing
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Solution Overview
Problem
Existing multichip packaging technologies face challenges in achieving low error rates and reducing latency in die-to-die (D2D) interconnects, which affect power consumption, buffer size, and system performance.
Innovation Solution
Implementing a valid signal in D2D interconnects to frame data transmission, detect errors, and reduce latency by using a pattern for the valid signal that allows for efficient clock gating and smaller retry buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction techniques such as CRC and retry are used to achieve low bit error rates, then system reliability is improved, but latency increases and buffer size requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-framing data with valid signals before transmission. The valid signal pattern is established in advance to indicate data boundaries and enable proactive error detection, allowing the receiver to identify and correct errors without waiting for full data reception or requiring extensive retry operations, thereby reducing latency while maintaining reliability
Solution Approach 2:
The valid signal acts as an intermediary element between the data transmitter and receiver. This intermediate signaling mechanism provides structural information about the data being transmitted, enabling the receiver to properly frame and validate data without requiring complex error correction protocols, thus reducing both latency and buffer requirements while maintaining error rates
2Productivity
If higher data rates are used to improve system performance, then productivity increases, but error rates increase and reliability decreases
Solution Approach 1:
The valid signal pattern is established in advance to provide structural information about data boundaries and transmission timing. This preliminary framing enables the receiver to correctly interpret high-speed data transmissions by knowing where data begins and ends, allowing higher data rates to be maintained with lower error rates since the receiver can properly synchronize and validate incoming data without relying solely on post-reception error correction
3Reliability
If larger retry buffers are used to handle errors, then reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The valid signal serves as an intermediary that provides transmission control information without requiring large buffers. By embedding framing and validation information in the valid signal itself, the system can detect and handle errors with minimal buffering requirements, reducing device complexity and power consumption associated with large retry buffers while maintaining reliable error handling capability
Data Source
AI summary
Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.