D6T In-Memory Computing Accelerator With Always-Linear Discharge
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Solution Overview
Problem
Existing IMC macro-modules face challenges in maintaining high computing density and energy efficiency due to sensitivity to read interference at low voltages, nonlinear current discharge, and overcomplicated digital steps, which limit parallelism and degrade performance.
Innovation Solution
A D6T IMC accelerator with a digital and analog bypass, utilizing always-linear discharge and reduced digital steps, featuring decoupled reading transistors, flexible capacitor structures, and a bias voltage time converter to maintain linear calculation and support parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional 6T SRAM cell is used for IMC, then memory storage function is provided, but read interference sensitivity increases at low voltage and parallelism is limited
Solution Approach 1:
The patent divides the single read port into two decoupled read ports (N2 and N3), allowing independent convolution calculations to be performed simultaneously. This segmentation enables parallel processing while maintaining reliable read operations at low voltages by separating the read paths.
Solution Approach 2:
The D6T bitcell is designed to serve multiple functions: it can perform both traditional memory storage and in-memory computing operations. The additional transistor enables the cell to function as both a storage element and a computing element with dual read ports, eliminating the need for separate memory and compute units.
2Manufacturing precision
If BL is pre-charged to high voltage to enable linear current generation, then MAC operation linearity is improved, but voltage overhead increases and nonlinear discharge persists
Solution Approach 1:
The patent changes the voltage parameter strategy by using moderate pre-charged voltages (0.3V-0.6V) instead of high voltages. The additional transistor and decoupled read port design enable linear current generation at these lower voltages, reducing voltage overhead while maintaining current linearity for accurate MAC operations.
Solution Approach 2:
The patent replaces the traditional high-voltage pre-charge mechanism with a transistor-based current control mechanism. The decoupled read transistors N2 and N3 provide controlled current paths that maintain linearity through their transistor characteristics rather than relying solely on high voltage pre-charging.
3Extent of automation
If digitally implemented IMC is used, then computing functionality is provided, but overcomplicated digital steps increase device complexity and reduce energy efficiency
Solution Approach 1:
The patent extracts the analog computing functionality from the digital processing pipeline. By enabling direct analog MAC operations in the memory cell with decoupled read ports, it removes the need for complex digital conversion and processing steps, reducing device complexity while maintaining computing functionality.
Solution Approach 2:
The patent merges the memory storage function and the computing function into a single unified structure. The D6T bitcell simultaneously performs storage and analog MAC operations, eliminating the need for separate digital processing units and reducing overall system complexity.
4Productivity
If more transistors are added to each bitcell to enable dual read ports, then parallelism and computing density are improved, but area overhead increases
Solution Approach 1:
The additional transistor in the D6T bitcell enables multi-functionality, allowing the same cell structure to provide both storage and dual read port capabilities. This universal design achieves improved computing density without proportionally increasing area overhead, as the extra transistor enables parallel operations within the extended bitcell structure.
Data Source
AI summary
A dual-six-transistor (D6T) in-memory computing (IMC) accelerator supporting always-linear discharge and reducing digital steps is provided. In the IMC accelerator, three effective techniques are proposed: (1) A D6T bitcell can reliably run at 0.4 V and enter a standby mode at 0.26 V, to support parallel processing of dual decoupled ports. (2) An always-linear discharge and convolution mechanism (ALDCM) not only reduces a voltage of a bit line (BL), but also keeps linear calculation throughout an entire voltage range of the BL. (3) A bypass of a bias voltage time converter (BVTC) reduces digital steps, but still keeps high energy efficiency and computing density at a low voltage. A measurement result of the IMC accelerator shows that the IMC accelerator achieves an average energy efficiency of 8918 TOPS/W (8b×8b), and an average computing density of 38.6 TOPS/mm2 (8b×8b) in a 55 nm CMOS technology.